From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qv1-f53.google.com (mail-qv1-f53.google.com [209.85.219.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B0AD38A72B for ; Wed, 19 Aug 2026 01:05:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.53 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787101540; cv=none; b=BTsL87Qw/Od2KL5cjSGlFxt4DCUI1OtgOlSEL5E0+JbOXwIaDj0JChXI2l9xXvtrfSpPyfGbYG5zXQ6EB/UvyZoKBzrff121RUR4vH8BqZ/m/UIYE5YsMddJdYldNdCfdg+GrQISOtle7JxvL+b21LCX9uxUGutY6YJ79gFjL/k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787101540; c=relaxed/simple; bh=UqrwUJeUkzsTv0rDMTVViGd15AGpV8soyywstDQ4sY0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uJcKxEpxIe33ikI32lOgYG9AzEudc1BP9at4W1CXI+bjh2gkq1B50ZaN9AAqasi4e+HDyhTFHhNYetoV6CR+mDukcs0Q80JmH1FtRM5XXFFb9KtGaaptxXABum94SkzNb89n5HJh7PhRkS5n3SGfZ4fvyn6Qmcdw4vmrdKPjEvE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=pCNzjaAI; arc=none smtp.client-ip=209.85.219.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pCNzjaAI" Received: by mail-qv1-f53.google.com with SMTP id 6a1803df08f44-8f1a8e914a9so5223126d6.1 for ; Tue, 18 Aug 2026 18:05:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787101537; x=1787706337; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=BLpEIzo5KtbJPDaJel4+Tkmj18nNDZ6vMDMBW3wK2ws=; b=pCNzjaAIIbzocXsHi1QV0qx2E+I7/gBg+EEcWnJY90nzPnWwuXXIoc4yspL8uCjuE3 25iH5UPJ1g2RfCXqcDy4BzxbdZSy2qpyY7rWzzQZ0HYEXPI/UUyBc0coa62PAMhtXSKu kLh8P4LLcFAzKZ1OUIeoZsP2bbRjbMrkseJUrCoZH4Pn1UnoVjNu6TBKydoU2Fff7lPr nO404ASC+12AVgZZjI4r/Ts77UfLGxZEtecdZbNEA1zyNqXSwyU6ku/2KNwIg1eRP6Cx TMyhoqK7qAbYjoY1BDwQmc/yxPPMscNhvfA6y9LrxC+gUBuN/Ua7YShUWh+xA84z9av/ MmcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787101537; x=1787706337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=BLpEIzo5KtbJPDaJel4+Tkmj18nNDZ6vMDMBW3wK2ws=; b=A+x6bsYr6MM9vS0ZwDWhu9Iq3PLooE8NPf6Fj+IjWbaJZ9zDlpOQBV3GSTSV2fIca/ fgmPVSRCcurCKktz5sKLOc3OCvnvEkS46NfTeAOzJvucnQuojTIYjSqxWSdWRaaViT6Y /5QEDfMNFl+wq5LXFJ3C1+kTKhYazFZNS0tbxyjrLjjxXJ/UNHmXnC8MgtvtlR0oY4kW YdghBDALa9mHBLs96uF2QbTIUnrZoV9wjwSH8xO5G3Zd09k2b+xGPRilz1k+HfVJ33lK 1LNxqWPvBUK6ihBcyz4/z62F6VGFcfJo41T2FulW7JaqAd0CNPFGc7UtZjXAt/CZQ3q2 ZBtA== X-Forwarded-Encrypted: i=1; AHgh+Rrd6225RUqssEXE7vSOqLjSg6WjSesVlaLnCysiIQRwVCxtf3xYKhlHfkEQQ1D/0MGNenHCL/sSNCt1@vger.kernel.org X-Gm-Message-State: AOJu0Yx7HFrCsSowA/cpJlgLrjpu3rOv3CD6KOznBhhsEyqGMnYpBt3G lgCEa652fGRPn8TPgimboLYoOeuZwrrvTGbiLMcImjHtg4q+30MGWDL5epN3Zw== X-Gm-Gg: AR+sD11liVGKjL8G8Ke/hHGLh/hrIwiSOzzQPE7tZ3/Ma492bzCULIYkx1vP8jhk5Gn 2WgVzdP8ck8dvyssPuSg1XFtd08c/dlZbzjQRmL9lVlHp/Kc5C3ahtjAaiYT/DXq4QZXG8Swk4G maYycDuLJEUWRtdDqPRNIqPAdUkyAwmZjrDHkAHJ9wKbiiuYoH4l8Il3lIa9eDS8Yk1k6IQp6lp +FX0N/Kw9GM195V7rFgmYDrjaRpmffLYjaFh1hk+PwdQUal63dE9RFk5jNJDIuqWLMqN91sFrYs qFk+9bxPyWEY6pul1JyAQ88ySHTytfxDwcUWlGM4Sga07JwPGtnhxqfMpkRvoEl32YFY3CCkMDp 0h2K3TxVIV9J531Dn3tFIXbTq5O1NZNWRNdd+w61nxELkyz0viJyw0pT53478w5br6G+MrHYqTq qiVIAzxq/FYJYdIN6cF+p80lX/ce3XT7MYNBZ1bqRJR5ETINTu7Ee2OYi/Dw== X-Received: by 2002:ac8:5a11:0:b0:52d:4ea9:b3d8 with SMTP id d75a77b69052e-52dd57bbf93mr11299101cf.3.1787101536904; Tue, 18 Aug 2026 18:05:36 -0700 (PDT) Received: from Turin ([187.15.143.241]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-90c5f29065bsm2398716d6.24.2026.08.18.18.05.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Aug 2026 18:05:36 -0700 (PDT) From: Nicholas Dudar To: bpf@vger.kernel.org Cc: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, johan.almbladh@anyfinetworks.com, paulburton@kernel.org, tsbogend@alpha.franken.de, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC bpf-next 1/2] bpf, mips: Factor register moves into helpers Date: Tue, 18 Aug 2026 21:05:22 -0400 Message-ID: <20260819010523.1057789-2-main.kalliope@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260819010523.1057789-1-main.kalliope@gmail.com> References: <20260819010523.1057789-1-main.kalliope@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Both MIPS JITs currently lower register MOV instructions directly in build_insn(), duplicating backend-specific handling for ALU32 and ALU64 destinations. Introduce 32-bit and 64-bit register-move helpers in each backend and route the existing MOV paths through them. Keep the verifier-inserted zero-extension marker on its dedicated path, so this is a behavior-preserving refactor. Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Nicholas Dudar --- arch/mips/net/bpf_jit_comp32.c | 22 ++++++++++++++++++---- arch/mips/net/bpf_jit_comp64.c | 18 +++++++++++++++--- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/arch/mips/net/bpf_jit_comp32.c b/arch/mips/net/bpf_jit_comp32.c index 40a878b672f5d..bfe73b023983e 100644 --- a/arch/mips/net/bpf_jit_comp32.c +++ b/arch/mips/net/bpf_jit_comp32.c @@ -190,6 +190,22 @@ static void emit_zext_ver(struct jit_context *ctx, const u8 dst[]) } } +/* Register move operation (32-bit) */ +static void emit_mov_r32(struct jit_context *ctx, const u8 dst[], + const u8 src[]) +{ + emit_mov_r(ctx, lo(dst), lo(src)); + emit_zext_ver(ctx, dst); +} + +/* Register move operation (64-bit) */ +static void emit_mov_r64(struct jit_context *ctx, const u8 dst[], + const u8 src[]) +{ + emit_mov_r(ctx, lo(dst), lo(src)); + emit_mov_r(ctx, hi(dst), hi(src)); +} + /* Load delay slot, if ISA mandates it */ static void emit_load_delay(struct jit_context *ctx) { @@ -1485,8 +1501,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) /* Special mov32 for zext */ emit_mov_i(ctx, hi(dst), 0); } else { - emit_mov_r(ctx, lo(dst), lo(src)); - emit_zext_ver(ctx, dst); + emit_mov_r32(ctx, dst, src); } break; /* dst = -dst */ @@ -1555,8 +1570,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) break; /* dst = src (64-bit) */ case BPF_ALU64 | BPF_MOV | BPF_X: - emit_mov_r(ctx, lo(dst), lo(src)); - emit_mov_r(ctx, hi(dst), hi(src)); + emit_mov_r64(ctx, dst, src); break; /* dst = -dst (64-bit) */ case BPF_ALU64 | BPF_NEG: diff --git a/arch/mips/net/bpf_jit_comp64.c b/arch/mips/net/bpf_jit_comp64.c index fa7e9aa37f498..45fee6f6b87e9 100644 --- a/arch/mips/net/bpf_jit_comp64.c +++ b/arch/mips/net/bpf_jit_comp64.c @@ -120,6 +120,19 @@ static void emit_zext_ver(struct jit_context *ctx, u8 dst) emit_zext(ctx, dst); } +/* Register move operation (32-bit) */ +static void emit_mov_r32(struct jit_context *ctx, u8 dst, u8 src) +{ + emit_mov_r(ctx, dst, src); + emit_zext_ver(ctx, dst); +} + +/* Register move operation (64-bit) */ +static void emit_mov_r64(struct jit_context *ctx, u8 dst, u8 src) +{ + emit_mov_r(ctx, dst, src); +} + /* dst = imm (64-bit) */ static void emit_mov_i64(struct jit_context *ctx, u8 dst, u64 imm64) { @@ -656,8 +669,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) /* Special mov32 for zext */ emit_zext(ctx, dst); } else { - emit_mov_r(ctx, dst, src); - emit_zext_ver(ctx, dst); + emit_mov_r32(ctx, dst, src); } break; /* dst = -dst */ @@ -742,7 +754,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) break; /* dst = src (64-bit) */ case BPF_ALU64 | BPF_MOV | BPF_X: - emit_mov_r(ctx, dst, src); + emit_mov_r64(ctx, dst, src); break; /* dst = -dst (64-bit) */ case BPF_ALU64 | BPF_NEG: