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HT=maildocker-contentspam033032062159; MF=support@armdesigner.com; NM=1; PH=DS; RN=17; RT=17; SR=0; TI=SMTPD_---.ir2CI.Z_1787127634; Received: from DESKTOP-F4DGRM2(mailfrom:support@armdesigner.com fp:SMTPD_---.ir2CI.Z_1787127634 cluster:ay29) by smtp.aliyun-inc.com; Wed, 19 Aug 2026 16:20:36 +0800 Date: Wed, 19 Aug 2026 16:20:35 +0800 Organization: boardcon From: support To: "royalnet026@gmail.com" , "Sandy Huang" , "Heiko Stuebner" , "Andy Yan" Cc: "royalnet026@gmail.com" , "Cristian Ciocaltea" , "Sebastian Reichel" , "Chaoyi Chen" , "Alexey Charkov" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "David Airlie" , "Simona Vetter" , dri-devel , linux-rockchip , linux-arm-kernel , linux-kernel Subject: Re: [PATCH v2] drm/rockchip: vop2: Scale the AXI clock to the bandwidth the mode needs References: <20260813094614.9072-1-royalnet026@gmail.com> X-Priority: 3 X-Has-Attach: no X-Mailer: Foxmail 7.2.25.563[cn] Mime-Version: 1.0 Message-ID: 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Hi Igor,&nbs= p;

Thanks for the thorough writeback =A1=AA good = to see the points land where they matter. 
Responses to your asked: 
1.  Permission to reference this= correspondence: Granted.  
You may cite the multi-CRTC tearing observation and the fanle= ss thermal data in the v3 cover letter.
2.  On-list participation when v3 drops: Yes, I will p= ost a summary on loads (dual HDMI + DP simultaneously active, transition from
three-screen to single-screen). (b) Thermal delta between 500 MHz and 800 MHz AC= LK on a fanless industrial chassis (RK3588J, ambient 60C, sustained SoC junction
+3-5C at 750 MHz). 1. Tested-by: Willing to commit. Our EM3588 bo= ard (RK3588, dual HDMI 2.1 + DP 1.4 + dual MIPI DSI, fanless, industrial deployment) is
exactly the multi-display bandwidth scenario your patch targets.&= nbsp; 

One caveat worth being upfront about:= our production kernel is 6.1 LTS (Rockchip BSP). I can apply v3 on top of that for the real-wor= ld deployment t= est =A1=AA 
multi-display stress + thermal logging over a 48h soak. If you need the test speci= fically on a mainline tree (v6.12+),
I can spin that up t= oo; it'll take a few days longer because I need to bring up the board on mainline first (no main= line DTS for our board
yet =A1=AA working on it). Which w= ould you prefer =A1=AA BSP 6.1 real-world, or mainline clean-room, or both? 1. v3 notification: = If you CC me when v3 is posted, I'll get on it immediately. 
Otherwise I'll watch the dri-deve= l list.  Good luck with the v3. Looking forward to seeing the FRL rel= ationship
stated explicitly and the commit_setup/commit_t= ail direction sorted. 

Best regards,

Owen
Boardcon Embedded Design
=0A
=0A
 
Date: 2026-08-13 17:45
<= div>To: Sandy Huang;= Heiko Stuebner; Andy Yan
Subject: [PATCH v2] drm/rockchi= p: vop2: Scale the AXI clock to the bandwidth the mode needs
VOP2 fetches the scanout data for all of its video ports ove= r a single
=0A
AXI clock.  On RK3588 that clock is pinned to= 500 MHz by the device tree
=0A
and nothing ever raises it, so a = mode whose pixel rate outruns what the
=0A
AXI clock can deliver = underruns the internal scanout FIFO.  The hardware
=0A
repor= ts this as POST_BUF_EMPTY and the picture is corrupted.
=0A
 = ;
=0A
3840x2160@120 over DisplayPort is such a mode.  Measur= ed on an Orange Pi
=0A
5 Plus by moving the rate at runtime while= the mode was up, with dclk
=0A
unchanged at 594 MHz throughout, = so that the AXI rate was the only
=0A
variable:
=0A
&nbs= p;
=0A
  500 MHz: ~594000 suppressed vop2_isr callbacks per = 5 s, corrupted
=0A
  750 MHz: no POST_BUF_EMPTY at all for t= he 42 s the phase lasted, clean
=0A
  500 MHz: ~607000 suppr= essed callbacks per 5 s, corrupted again
=0A
 
=0A
= Both transitions are immediate.  Heiko Stuebner reports the same=0A
starvation on different hardware [1].
=0A
 
= =0A
The requirement follows each port's pixel rate rather than its int= erface
=0A
clock, and it is per port rather than aggregate. = Two measurements at
=0A
500 MHz pin that down:
=0A
&nbs= p;
=0A
  - a single port scanning out 3840x2160@120 underrun= s, while the same
=0A
    composed pixel rate spre= ad over three ports - 3840x2160@60 on one
=0A
    = and 3840x2160@30 on two others - is clean for a minute with no
=0A    underrun on any of them.  The totals are equal t= o the pixel:
=0A
    3840*2160*120 =3D=3D 3840*216= 0*(60+30+30).
=0A
 
=0A
  - 3840x2160@60 is cl= ean where 3840x2160@120 is not, although both run
=0A
  = ;  dclk at 594 MHz on this board: the 120 Hz link is YCbCr 4:2:0, whi= ch
=0A
    halves dclk without halving the rate at= which the port consumes
=0A
    pixels.
=0A<= div> 
=0A
So the condition belongs on each video port's own = crtc_clock.  Summing
=0A
across ports would be wrong, and ke= ying on dclk would miss 4:2:0
=0A
entirely.  The threshold s= its between the measured points: 3840x2160@60
=0A
(594000 kHz) an= d 2560x1440@144 (about 586000 kHz) are both clean at the
=0A
defa= ult rate, 3840x2160@120 (1188000 kHz) is not.
=0A
 
=0A=
Track the requirement as a global atomic state object rather than by<= /div>=0A
walking the CRTC list when the rate is applied.  Each CR= TC records what
=0A
it needs during its own atomic check, and the= rate applied is the
=0A
maximum over the ports.  Going thro= ugh the atomic state is what makes
=0A
this safe: a commit only e= ver writes the entry for a CRTC it holds a
=0A
lock for, and neve= r reads the state of a CRTC that a concurrent commit
=0A
may be s= wapping underneath it.  The rate the platform set up is used as
= =0A
the lower bound, so a board that already configures a higher rate = keeps
=0A
it.
=0A
 
=0A
Tested on the same= board on drm-misc-next plus the dw-dp and Rockchip
=0A
USBDP PHY= series, which DisplayPort Alt Mode needs in order to come up
=0Aat all: 3840x2160@120 selects 750 MHz and runs with no underrun,
=0A=
dropping to 3840x2160@60 returns the clock to 500 MHz and stays clean= ,
=0A
and going back raises it again.  On that same kernel w= ithout this patch
=0A
the output shows no picture at any mode.=0A
 
=0A
Link: https://lore.kernel.org/all/202608081= 04240.13776-1-royalnet026@gmail.com/
=0A
Link: https://lore.kerne= l.org/all/20767137.geO5KgaWL5@diego/ [1]
=0A
Signed-off-by: Igor = Paunovic <royalnet026@gmail.com>
=0A
---
=0A
v2:=0A
- Reworked how the requirement is tracked.  v1 computed = the rate by walking
=0A
   the CRTC list at the point i= t applied it, which read the state of CRTCs the
=0A
   = commit holds no lock for; a concurrent non-blocking commit on another CRTC=
=0A
   can swap and free that state underneath.  = Caught by the Sashiko AI review
=0A
   [2] before anyon= e had to trip over it.  v2 has each CRTC record its own
=0A
=    requirement in a global atomic state object during its own at= omic check and
=0A
   takes the maximum over the ports,= so a commit never reads state it does not
=0A
   own.&= nbsp; The shape follows vc4's handling of its core clock, which is the sam= e
=0A
   problem.
=0A
- Retested on hardware = with the new mechanism, since the old measurement no
=0A
 &n= bsp; longer applies to it: 3840x2160@120 selects 750 MHz, dropping to=0A
   3840x2160@60 returns the clock to 500 MHz, and going= back raises it again,
=0A
   with no POST_BUF_EMPTY in= any phase and nothing failing in the atomic path.
=0A
 =0A
v1: https://lore.kernel.org/all/20260812104909.6390-1-royalnet02= 6@gmail.com/
=0A
[2] https://lore.kernel.org/all/20260812105649.3= 9CBA1F000E9@smtp.kernel.org/
=0A
drivers/gpu/drm/rockchip/rockch= ip_drm_vop2.c | 107 +++++++++++++++++++
=0A
drivers/gpu/drm/rock= chip/rockchip_drm_vop2.h |  19 ++++
=0A
2 files changed, 12= 6 insertions(+)
=0A
 
=0A
diff --git a/drivers/gpu/= drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_v= op2.c
=0A
index 4cce3e336f5b..fdee08042ac7 100644
=0A
--= - a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
=0A
+++ b/driver= s/gpu/drm/rockchip/rockchip_drm_vop2.c
=0A
@@ -104,6 +104,20 @@ e= num vop2_afbc_format {
=0A
=0A
#define VOP2_MAX_DCLK_= RATE 600000000UL
=0A
=0A
+/*
=0A
+ * All vid= eo ports fetch their scanout data over a single AXI clock.  The
= =0A
+ * hardware buffers that data in an internal FIFO which is draine= d at the
=0A
+ * pixel rate, so a mode whose pixel rate outruns t= he fill rate underruns the
=0A
+ * FIFO, which the hardware repor= ts as POST_BUF_EMPTY and which shows up as a
=0A
+ * corrupted im= age.  Raise the AXI clock for modes that need it.
=0A
+ *=0A
+ * The requirement follows the pixel rate rather than the inte= rface clock: a
=0A
+ * YCbCr 4:2:0 link halves dclk but not the r= ate at which the video port
=0A
+ * consumes pixels.
=0A+ */
=0A
+#define VOP2_ACLK_RATE_HIGH 750000000UL
=0A
= +#define VOP2_HIGH_BW_PIXCLK_KHZ 1000000
=0A
+
=0A
/*<= /div>=0A
  * bus-format types.
=0A
  */
=0A@@ -1008,6 +1022,72 @@ static bool vop2_gamma_lut_in_use(struct vop2 *vo= p2, struct vop2_video_port *vp)
=0A
return gamma_en_vp_id !=3D = nr_vps && gamma_en_vp_id !=3D vp->id;
=0A
}
=0A<= div>
=0A
+static struct drm_private_state *
=0A
+vop2_a= clk_create_state(struct drm_private_obj *obj)
=0A
+{
=0A+ struct vop2_aclk_state *state;
=0A
+
=0A
+ state =3D = kzalloc_obj(*state);
=0A
+ if (!state)
=0A
+ return ERR= _PTR(-ENOMEM);
=0A
+
=0A
+ return &state->base;=0A
+}
=0A
+
=0A
+static struct drm_private_stat= e *
=0A
+vop2_aclk_duplicate_state(struct drm_private_obj *obj)=0A
+{
=0A
+ struct vop2_aclk_state *state;
=0A
= +
=0A
+ state =3D kmemdup(obj->state, sizeof(*state), GFP_KERN= EL);
=0A
+ if (!state)
=0A
+ return NULL;
=0A
= +
=0A
+ __drm_atomic_helper_private_obj_duplicate_state(obj, &= ;state->base);
=0A
+
=0A
+ return &state->base= ;
=0A
+}
=0A
+
=0A
+static void vop2_aclk_destr= oy_state(struct drm_private_obj *obj,
=0A
+    = struct drm_private_state *state)
=0A
+{
=0A
+ kfree(to_= vop2_aclk_state(state));
=0A
+}
=0A
+
=0A
+stat= ic const struct drm_private_state_funcs vop2_aclk_state_funcs =3D {
= =0A
+ .atomic_create_state =3D vop2_aclk_create_state,
=0A
+ = .atomic_duplicate_state =3D vop2_aclk_duplicate_state,
=0A
+ .ato= mic_destroy_state =3D vop2_aclk_destroy_state,
=0A
+};
=0A+
=0A
+/* The rate that satisfies every video port, never belo= w the platform's own. */
=0A
+static unsigned long vop2_aclk_rate= (struct vop2 *vop2,
=0A
+     const struct vop2= _aclk_state *aclk_state)
=0A
+{
=0A
+ unsigned long rate= =3D vop2->aclk_rate_normal;
=0A
+ unsigned int i;
=0A+
=0A
+ for (i =3D 0; i < vop2->data->nr_vps; i++)=0A
+ rate =3D max(rate, aclk_state->vp_rate[i]);
=0A
+=
=0A
+ return rate;
=0A
+}
=0A
+
=0A
+= static void vop2_apply_aclk_rate(struct vop2 *vop2, struct drm_atomic_comm= it *state)
=0A
+{
=0A
+ struct drm_private_state *priv_s= tate;
=0A
+
=0A
+ if (vop2->version !=3D VOP_VERSION_= RK3588)
=0A
+ return;
=0A
+
=0A
+ priv_state = =3D drm_atomic_get_new_private_obj_state(state, &vop2->aclk_obj);=0A
+ if (!priv_state)
=0A
+ return;
=0A
+=0A
+ clk_set_rate(vop2->aclk,
=0A
+    &= nbsp; vop2_aclk_rate(vop2, to_vop2_aclk_state(priv_state)));
=0A
= +}
=0A
+
=0A
static void vop2_crtc_atomic_disable(struc= t drm_crtc *crtc,
=0A
     struct drm_at= omic_commit *state)
=0A
{
=0A
@@ -1053,6 +1133,8 @@ sta= tic void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
=0A
if= (!vop2->enable_count)
=0A
vop2_disable(vop2);
=0A
=0A
+ vop2_apply_aclk_rate(vop2, state);
=0A
+
= =0A
vop2_unlock(vop2);
=0A
=0A
if (crtc->st= ate->event && !crtc->state->active) {
=0A
@@ -17= 80,6 +1862,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,=
=0A
=0A
vop2_lock(vop2);
=0A
=0A+ vop2_apply_aclk_rate(vop2, state);
=0A
+
=0A
ret = =3D clk_prepare_enable(vp->dclk);
=0A
if (ret < 0) {=0A
drm_err(vop2->drm, "failed to enable dclk for video port%d = - %d\n",
=0A
@@ -1993,6 +2077,20 @@ static int vop2_crtc_atomic_c= heck(struct drm_crtc *crtc,
=0A
if (ret)
=0A
return= ret;
=0A
=0A
+ if (vp->vop2->version =3D=3D VOP= _VERSION_RK3588) {
=0A
+ struct drm_private_state *priv_state;=0A
+
=0A
+ priv_state =3D drm_atomic_get_private_obj_st= ate(state,
=0A
+       &vp->= ;vop2->aclk_obj);
=0A
+ if (IS_ERR(priv_state))
=0A
= + return PTR_ERR(priv_state);
=0A
+
=0A
+ to_vop2_acl= k_state(priv_state)->vp_rate[vp->id] =3D
=0A
+ crtc_state= ->active &&
=0A
+ crtc_state->adjusted_mode.crtc_= clock > VOP2_HIGH_BW_PIXCLK_KHZ ?
=0A
+ VOP2_ACLK_RATE_HIGH = : 0;
=0A
+ }
=0A
+
=0A
drm_atomic_crtc_state_= for_each_plane(plane, crtc_state)
=0A
nplanes++;
=0A
=
=0A
@@ -2875,6 +2973,8 @@ static int vop2_bind(struct device *d= ev, struct device *master, void *data)
=0A
return dev_err_prob= e(drm->dev, PTR_ERR(vop2->aclk),
=0A
   = ;  "failed to get aclk source\n");
=0A
=0A
+ vop2= ->aclk_rate_normal =3D clk_get_rate(vop2->aclk);
=0A
+=0A
vop2->pclk =3D devm_clk_get_optional(vop2->dev, "pclk_vop= ");
=0A
if (IS_ERR(vop2->pclk))
=0A
return dev_e= rr_probe(drm->dev, PTR_ERR(vop2->pclk),
=0A
@@ -2944,6 +304= 4,11 @@ static int vop2_bind(struct device *dev, struct device *master, vo= id *data)
=0A
=0A
rockchip_drm_dma_init_device(vop2-= >drm, vop2->dev);
=0A
=0A
+ ret =3D drm_atomic_p= rivate_obj_init(vop2->drm, &vop2->aclk_obj,
=0A
+ &= nbsp; &vop2_aclk_state_funcs);
=0A
+ if (ret)
=0A
+ = goto err_crtcs;
=0A
+
=0A
pm_runtime_enable(&pdev= ->dev);
=0A
=0A
return 0;
=0A
@@ -2960,6= +3065,8 @@ static void vop2_unbind(struct device *dev, struct device *mas= ter, void *data)
=0A
=0A
pm_runtime_disable(dev);=0A
=0A
+ drm_atomic_private_obj_fini(&vop2->aclk= _obj);
=0A
+
=0A
if (vop2->rgb)
=0A
roc= kchip_rgb_fini(vop2->rgb);
=0A
=0A
diff --git a/dri= vers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockc= hip_drm_vop2.h
=0A
index ffcb39c130aa..df148dc61703 100644
= =0A
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
=0A
++= + b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
=0A
@@ -8,6 +8,7= @@
=0A
#define _ROCKCHIP_DRM_VOP2_H
=0A
=0A #include <linux/regmap.h>
=0A
+#include <drm/drm_atomi= c.h>
=0A
#include <drm/drm_modes.h>
=0A
#incl= ude <dt-bindings/soc/rockchip,vop2.h>
=0A
#include "rockch= ip_drm_drv.h"
=0A
@@ -286,6 +287,21 @@ struct vop2_data {
= =0A
unsigned int soc_id;
=0A
};
=0A
=0A+/*
=0A
+ * The AXI clock is shared by every video port, so the= rate it has to run at is
=0A
+ * a property of the device rather= than of one CRTC.  Track it as a global
=0A
+ * atomic stat= e object: each CRTC records its own requirement during atomic
=0A+ * check, and the rate applied is the maximum over the ports.  Goin= g through
=0A
+ * the atomic state is what makes this safe - a co= mmit never reads the state of
=0A
+ * a CRTC it does not hold a l= ock for.
=0A
+ */
=0A
+struct vop2_aclk_state {
=0A=
+ struct drm_private_state base;
=0A
+ unsigned long vp_rate= [ROCKCHIP_MAX_CRTC];
=0A
+};
=0A
+
=0A
+#define= to_vop2_aclk_state(x) container_of(x, struct vop2_aclk_state, base)
= =0A
+
=0A
struct vop2 {
=0A
u32 version;
=0A=
struct device *dev;
=0A
@@ -326,6 +342,9 @@ struct vop2 {<= /div>=0A
unsigned int enable_count;
=0A
struct clk *hclk;=
=0A
struct clk *aclk;
=0A
+ /* AXI clock rate set up = by the platform, used as the lower bound. */
=0A
+ unsigned long = aclk_rate_normal;
=0A
+ struct drm_private_obj aclk_obj;
=0A=
struct clk *pclk;
=0A
struct clk *pll_hdmiphy0;
=0A=
struct clk *pll_hdmiphy1;
=0A
--
=0A
2.43.0=0A
 
=0A
 
=0A
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From: Igor Paunovic <royalnet0= 26@gmail.com>
=0A
To: Sandy Huang <hjc@rock-chips.com>,<= /div>=0A
Heiko Stuebner <heiko@sntech.de>,
=0A
Andy Y= an <andy.yan@rock-chips.com>
=0A
Subject: [PATCH v2] drm/ro= ckchip: vop2: Scale the AXI clock to the bandwidth the mode needs
=0A=
Date: Thu, 13 Aug 2026 11:45:56 +0200
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X-CR= M114-Status: GOOD (  33.39  )
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List-Id: Upstream kernel work for Rockc= hip platforms <linux-rockchip.lists.infradead.org>
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Cc: Igor Paunovic <royalnet= 026@gmail.com>, Simona Vetter <simona@ffwll.ch>, linux-kernel@vge= r.kernel.org, Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,= Sebastian Reichel <sebastian.reichel@collabora.com>, Maxime Ripard = <mripard@kernel.org>, Chaoyi Chen <chaoyi.chen@rock-chips.com>= , Alexey Charkov <alchark@flipper.net>, linux-rockchip@lists.infrade= ad.org, dri-devel@lists.freedesktop.org, Thomas Zimmermann <tzimmermann= @suse.de>, David Airlie <airlied@gmail.com>, linux-arm-kernel@lis= ts.infradead.org
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Content-Transfer-Encoding: 7bit
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Sender: "Linu= x-rockchip" <linux-rockchip-bounces@lists.infradead.org>
=0AErrors-To: linux-rockchip-bounces+linux-rockchip=3Darchiver.kernel.org@l= ists.infradead.org
=0A
 
=0A
VOP2 fetches the scano= ut data for all of its video ports over a single
=0A
AXI clock.&n= bsp; On RK3588 that clock is pinned to 500 MHz by the device tree
=0A=
and nothing ever raises it, so a mode whose pixel rate outruns what t= he
=0A
AXI clock can deliver underruns the internal scanout FIFO.=   The hardware
=0A
reports this as POST_BUF_EMPTY and the pi= cture is corrupted.
=0A
 
=0A
3840x2160@120 over Di= splayPort is such a mode.  Measured on an Orange Pi
=0A
5 Pl= us by moving the rate at runtime while the mode was up, with dclk
=0A=
unchanged at 594 MHz throughout, so that the AXI rate was the only=0A
variable:
=0A
 
=0A
  500 MHz: ~594= 000 suppressed vop2_isr callbacks per 5 s, corrupted
=0A
  7= 50 MHz: no POST_BUF_EMPTY at all for the 42 s the phase lasted, clean=0A
  500 MHz: ~607000 suppressed callbacks per 5 s, corrupted a= gain
=0A
 
=0A
Both transitions are immediate. = ; Heiko Stuebner reports the same
=0A
starvation on different har= dware [1].
=0A
 
=0A
The requirement follows each p= ort's pixel rate rather than its interface
=0A
clock, and it is p= er port rather than aggregate.  Two measurements at
=0A
500 = MHz pin that down:
=0A
 
=0A
  - a single port= scanning out 3840x2160@120 underruns, while the same
=0A
 &= nbsp;  composed pixel rate spread over three ports - 3840x2160@60 on = one
=0A
    and 3840x2160@30 on two others - is cl= ean for a minute with no
=0A
    underrun on any o= f them.  The totals are equal to the pixel:
=0A
  =   3840*2160*120 =3D=3D 3840*2160*(60+30+30).
=0A
 =0A
  - 3840x2160@60 is clean where 3840x2160@120 is not, althou= gh both run
=0A
    dclk at 594 MHz on this board:= the 120 Hz link is YCbCr 4:2:0, which
=0A
    hal= ves dclk without halving the rate at which the port consumes
=0A
=     pixels.
=0A
 
=0A
So the conditi= on belongs on each video port's own crtc_clock.  Summing
=0Aacross ports would be wrong, and keying on dclk would miss 4:2:0
=0A=
entirely.  The threshold sits between the measured points: 3840x= 2160@60
=0A
(594000 kHz) and 2560x1440@144 (about 586000 kHz) are= both clean at the
=0A
default rate, 3840x2160@120 (1188000 kHz) = is not.
=0A
 
=0A
Track the requirement as a global= atomic state object rather than by
=0A
walking the CRTC list whe= n the rate is applied.  Each CRTC records what
=0A
it needs = during its own atomic check, and the rate applied is the
=0A
maxi= mum over the ports.  Going through the atomic state is what makes=0A
this safe: a commit only ever writes the entry for a CRTC it hol= ds a
=0A
lock for, and never reads the state of a CRTC that a con= current commit
=0A
may be swapping underneath it.  The rate = the platform set up is used as
=0A
the lower bound, so a board th= at already configures a higher rate keeps
=0A
it.
=0A
&n= bsp;
=0A
Tested on the same board on drm-misc-next plus the dw-dp= and Rockchip
=0A
USBDP PHY series, which DisplayPort Alt Mode ne= eds in order to come up
=0A
at all: 3840x2160@120 selects 750 MHz= and runs with no underrun,
=0A
dropping to 3840x2160@60 returns = the clock to 500 MHz and stays clean,
=0A
and going back raises i= t again.  On that same kernel without this patch
=0A
the out= put shows no picture at any mode.
=0A
 
=0A
Link: h= ttps://lore.kernel.org/all/20260808104240.13776-1-royalnet026@gmail.com/=0A
Link: https://lore.kernel.org/all/20767137.geO5KgaWL5@diego/ [= 1]
=0A
Signed-off-by: Igor Paunovic <royalnet026@gmail.com>=
=0A
---
=0A
v2:
=0A
- Reworked how the requir= ement is tracked.  v1 computed the rate by walking
=0A
 = ;  the CRTC list at the point it applied it, which read the state of = CRTCs the
=0A
   commit holds no lock for; a concurrent= non-blocking commit on another CRTC
=0A
   can swap an= d free that state underneath.  Caught by the Sashiko AI review
= =0A
   [2] before anyone had to trip over it.  v2 has e= ach CRTC record its own
=0A
   requirement in a global = atomic state object during its own atomic check and
=0A
 &nb= sp; takes the maximum over the ports, so a commit never reads state it doe= s not
=0A
   own.  The shape follows vc4's handlin= g of its core clock, which is the same
=0A
   problem.<= /div>=0A
- Retested on hardware with the new mechanism, since the old= measurement no
=0A
   longer applies to it: 3840x2160@= 120 selects 750 MHz, dropping to
=0A
   3840x2160@60 re= turns the clock to 500 MHz, and going back raises it again,
=0A
&= nbsp;  with no POST_BUF_EMPTY in any phase and nothing failing in the= atomic path.
=0A
 
=0A
v1: https://lore.kernel.org= /all/20260812104909.6390-1-royalnet026@gmail.com/
=0A
[2] https:/= /lore.kernel.org/all/20260812105649.39CBA1F000E9@smtp.kernel.org/
=0A=
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 107 +++++++++++++++++= ++
=0A
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h |  19 += +++
=0A
2 files changed, 126 insertions(+)
=0A
 =0A
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/dr= ivers/gpu/drm/rockchip/rockchip_drm_vop2.c
=0A
index 4cce3e336f5b= ..fdee08042ac7 100644
=0A
--- a/drivers/gpu/drm/rockchip/rockchip= _drm_vop2.c
=0A
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.= c
=0A
@@ -104,6 +104,20 @@ enum vop2_afbc_format {
=0A
=
=0A
#define VOP2_MAX_DCLK_RATE 600000000UL
=0A
=0A
+/*
=0A
+ * All video ports fetch their scanout data ove= r a single AXI clock.  The
=0A
+ * hardware buffers that dat= a in an internal FIFO which is drained at the
=0A
+ * pixel rate,= so a mode whose pixel rate outruns the fill rate underruns the
=0A+ * FIFO, which the hardware reports as POST_BUF_EMPTY and which shows = up as a
=0A
+ * corrupted image.  Raise the AXI clock for mo= des that need it.
=0A
+ *
=0A
+ * The requirement follow= s the pixel rate rather than the interface clock: a
=0A
+ * YCbCr= 4:2:0 link halves dclk but not the rate at which the video port
=0A<= div>+ * consumes pixels.
=0A
+ */
=0A
+#define VOP2_ACLK= _RATE_HIGH 750000000UL
=0A
+#define VOP2_HIGH_BW_PIXCLK_KHZ 100= 0000
=0A
+
=0A
/*
=0A
  * bus-format type= s.
=0A
  */
=0A
@@ -1008,6 +1022,72 @@ static bool = vop2_gamma_lut_in_use(struct vop2 *vop2, struct vop2_video_port *vp)
= =0A
return gamma_en_vp_id !=3D nr_vps && gamma_en_vp_id !=3D= vp->id;
=0A
}
=0A
=0A
+static struct drm= _private_state *
=0A
+vop2_aclk_create_state(struct drm_private_o= bj *obj)
=0A
+{
=0A
+ struct vop2_aclk_state *state;=0A
+
=0A
+ state =3D kzalloc_obj(*state);
=0A
+ i= f (!state)
=0A
+ return ERR_PTR(-ENOMEM);
=0A
+
= =0A
+ return &state->base;
=0A
+}
=0A
+
= =0A
+static struct drm_private_state *
=0A
+vop2_aclk_duplica= te_state(struct drm_private_obj *obj)
=0A
+{
=0A
+ struc= t vop2_aclk_state *state;
=0A
+
=0A
+ state =3D kmemdup(= obj->state, sizeof(*state), GFP_KERNEL);
=0A
+ if (!state)=0A
+ return NULL;
=0A
+
=0A
+ __drm_atomic_helpe= r_private_obj_duplicate_state(obj, &state->base);
=0A
+=0A
+ return &state->base;
=0A
+}
=0A
+=0A
+static void vop2_aclk_destroy_state(struct drm_private_obj *ob= j,
=0A
+     struct drm_private_state *state)=0A
+{
=0A
+ kfree(to_vop2_aclk_state(state));
=0A+}
=0A
+
=0A
+static const struct drm_private_state_f= uncs vop2_aclk_state_funcs =3D {
=0A
+ .atomic_create_state =3D v= op2_aclk_create_state,
=0A
+ .atomic_duplicate_state =3D vop2_acl= k_duplicate_state,
=0A
+ .atomic_destroy_state =3D vop2_aclk_dest= roy_state,
=0A
+};
=0A
+
=0A
+/* The rate that = satisfies every video port, never below the platform's own. */
=0A+static unsigned long vop2_aclk_rate(struct vop2 *vop2,
=0A
+ =     const struct vop2_aclk_state *aclk_state)
=0A+{
=0A
+ unsigned long rate =3D vop2->aclk_rate_normal;=0A
+ unsigned int i;
=0A
+
=0A
+ for (i =3D 0; i &= lt; vop2->data->nr_vps; i++)
=0A
+ rate =3D max(rate, aclk= _state->vp_rate[i]);
=0A
+
=0A
+ return rate;
= =0A
+}
=0A
+
=0A
+static void vop2_apply_aclk_rate(s= truct vop2 *vop2, struct drm_atomic_commit *state)
=0A
+{
= =0A
+ struct drm_private_state *priv_state;
=0A
+
=0A+ if (vop2->version !=3D VOP_VERSION_RK3588)
=0A
+ return;<= /div>=0A
+
=0A
+ priv_state =3D drm_atomic_get_new_private_ob= j_state(state, &vop2->aclk_obj);
=0A
+ if (!priv_state)=0A
+ return;
=0A
+
=0A
+ clk_set_rate(vop2->= aclk,
=0A
+      vop2_aclk_rate(vop2, to_vop= 2_aclk_state(priv_state)));
=0A
+}
=0A
+
=0A
s= tatic void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
=0A
=      struct drm_atomic_commit *state)
=0A
= {
=0A
@@ -1053,6 +1133,8 @@ static void vop2_crtc_atomic_disable= (struct drm_crtc *crtc,
=0A
if (!vop2->enable_count)
= =0A
vop2_disable(vop2);
=0A
=0A
+ vop2_apply_ac= lk_rate(vop2, state);
=0A
+
=0A
vop2_unlock(vop2);=0A
=0A
if (crtc->state->event && !crtc-&= gt;state->active) {
=0A
@@ -1780,6 +1862,8 @@ static void vop2= _crtc_atomic_enable(struct drm_crtc *crtc,
=0A
=0A
v= op2_lock(vop2);
=0A
=0A
+ vop2_apply_aclk_rate(vop2, s= tate);
=0A
+
=0A
ret =3D clk_prepare_enable(vp->dcl= k);
=0A
if (ret < 0) {
=0A
drm_err(vop2->drm,= "failed to enable dclk for video port%d - %d\n",
=0A
@@ -1993,6 = +2077,20 @@ static int vop2_crtc_atomic_check(struct drm_crtc *crtc,
= =0A
if (ret)
=0A
return ret;
=0A
=0A+ if (vp->vop2->version =3D=3D VOP_VERSION_RK3588) {
=0A
+= struct drm_private_state *priv_state;
=0A
+
=0A
+ pri= v_state =3D drm_atomic_get_private_obj_state(state,
=0A
+ &= nbsp;     &vp->vop2->aclk_obj);
=0A+ if (IS_ERR(priv_state))
=0A
+ return PTR_ERR(priv_state);=0A
+
=0A
+ to_vop2_aclk_state(priv_state)->vp_rate[v= p->id] =3D
=0A
+ crtc_state->active &&
=0A+ crtc_state->adjusted_mode.crtc_clock > VOP2_HIGH_BW_PIXCLK_KH= Z ?
=0A
+ VOP2_ACLK_RATE_HIGH : 0;
=0A
+ }
=0A+
=0A
drm_atomic_crtc_state_for_each_plane(plane, crtc_state)=
=0A
nplanes++;
=0A
=0A
@@ -2875,6 +2973,8= @@ static int vop2_bind(struct device *dev, struct device *master, void *= data)
=0A
return dev_err_probe(drm->dev, PTR_ERR(vop2->a= clk),
=0A
     "failed to get aclk sourc= e\n");
=0A
=0A
+ vop2->aclk_rate_normal =3D clk_get= _rate(vop2->aclk);
=0A
+
=0A
vop2->pclk =3D devm= _clk_get_optional(vop2->dev, "pclk_vop");
=0A
if (IS_ERR(vop= 2->pclk))
=0A
return dev_err_probe(drm->dev, PTR_ERR(vop= 2->pclk),
=0A
@@ -2944,6 +3044,11 @@ static int vop2_bind(stru= ct device *dev, struct device *master, void *data)
=0A
=0A=
rockchip_drm_dma_init_device(vop2->drm, vop2->dev);
=0A<= div>
=0A
+ ret =3D drm_atomic_private_obj_init(vop2->drm, &am= p;vop2->aclk_obj,
=0A
+   &vop2_aclk_state_funcs)= ;
=0A
+ if (ret)
=0A
+ goto err_crtcs;
=0A
+=0A
pm_runtime_enable(&pdev->dev);
=0A
= =0A
return 0;
=0A
@@ -2960,6 +3065,8 @@ static void vop2_un= bind(struct device *dev, struct device *master, void *data)
=0A
=
=0A
pm_runtime_disable(dev);
=0A
=0A
+ drm= _atomic_private_obj_fini(&vop2->aclk_obj);
=0A
+
=0A<= div> if (vop2->rgb)
=0A
rockchip_rgb_fini(vop2->rgb);=0A
=0A
diff --git a/drivers/gpu/drm/rockchip/rockchip_= drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
=0A
ind= ex ffcb39c130aa..df148dc61703 100644
=0A
--- a/drivers/gpu/drm/ro= ckchip/rockchip_drm_vop2.h
=0A
+++ b/drivers/gpu/drm/rockchip/roc= kchip_drm_vop2.h
=0A
@@ -8,6 +8,7 @@
=0A
#define _ROCKC= HIP_DRM_VOP2_H
=0A
=0A
#include <linux/regmap.h>= ;
=0A
+#include <drm/drm_atomic.h>
=0A
#include &= lt;drm/drm_modes.h>
=0A
#include <dt-bindings/soc/rockchip= ,vop2.h>
=0A
#include "rockchip_drm_drv.h"
=0A
@@ -2= 86,6 +287,21 @@ struct vop2_data {
=0A
unsigned int soc_id;=0A
};
=0A
=0A
+/*
=0A
+ * The AXI clo= ck is shared by every video port, so the rate it has to run at is
=0A=
+ * a property of the device rather than of one CRTC.  Track it = as a global
=0A
+ * atomic state object: each CRTC records its ow= n requirement during atomic
=0A
+ * check, and the rate applied i= s the maximum over the ports.  Going through
=0A
+ * the ato= mic state is what makes this safe - a commit never reads the state of=0A
+ * a CRTC it does not hold a lock for.
=0A
+ */
= =0A
+struct vop2_aclk_state {
=0A
+ struct drm_private_state = base;
=0A
+ unsigned long vp_rate[ROCKCHIP_MAX_CRTC];
=0A+};
=0A
+
=0A
+#define to_vop2_aclk_state(x) container= _of(x, struct vop2_aclk_state, base)
=0A
+
=0A
struct v= op2 {
=0A
u32 version;
=0A
struct device *dev;
= =0A
@@ -326,6 +342,9 @@ struct vop2 {
=0A
unsigned int enab= le_count;
=0A
struct clk *hclk;
=0A
struct clk *aclk= ;
=0A
+ /* AXI clock rate set up by the platform, used as the low= er bound. */
=0A
+ unsigned long aclk_rate_normal;
=0A
+= struct drm_private_obj aclk_obj;
=0A
struct clk *pclk;
= =0A
struct clk *pll_hdmiphy0;
=0A
struct clk *pll_hdmiphy= 1;
=0A
--
=0A
2.43.0
=0A
 
=0A
&= nbsp;
=0A
_______________________________________________
= =0A
Linux-rockchip mailing list
=0A
Linux-rockchip@lists.infr= adead.org
=0A
http://lists.infradead.org/mailman/listinfo/linux-r= ockchip
=0A
 
=0A
=0A ------=_001_NextPart707658515182_=------