Re: [PATCH v3 1/2] gpu: nova-core: fix barrier usage in CPU->GSP messaging path

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

Pre-existing issues:
- [High] Missing LOAD->LOAD DMA memory barrier in the GSP->CPU receive path, risking stale data reads.
- [High] Use of CPU-centric `fence(Ordering::SeqCst)` instead of a DMA barrier in `advance_cpu_read_ptr`.
--

--- Patch [1]: [PATCH v3 1/2] gpu: nova-core: fix barrier usage in CPU->GSP messaging path ---
commit 4ff1d5624b6cb01f484147f0e0780dbdb7b0b09e
Author: Gary Guo <gary@garyguo.net>

gpu: nova-core: fix barrier usage in CPU->GSP messaging path

In the CPU->GSP messaging path, the code reads the read pointer from GSP,
writes the command, advances the write pointer, and then notifies the GSP.
This commit adds a load-to-store ordering, and moves a store-to-store
ordering to occur before the write pointer advance.

> diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/cmdq.rs
> index 6da728201281b..70674d2d0f77e 100644
> --- a/drivers/gpu/nova-core/gsp/cmdq.rs
> +++ b/drivers/gpu/nova-core/gsp/cmdq.rs
[ ... ]
> @@ -450,9 +459,6 @@ fn advance_cpu_write_ptr(&mut self, elem_count: u32) {
>          let tx = io_project!(self.0, .cpuq.tx);
>          let wptr = MsgqTxHeader::write_ptr(tx).wrapping_add(elem_count) % MSGQ_NUM_PAGES;
>          MsgqTxHeader::set_write_ptr(tx, wptr);
> -
> -        // Ensure all command data is visible before triggering the GSP read.
> -        fence(Ordering::SeqCst);
>      }
>  }

[Severity: High]
This is a pre-existing issue, but I noticed there might be a missing
load-to-load DMA memory barrier in the GSP to CPU receive path.

When the driver receives a message via wait_for_msg(), it polls the GSP
write pointer by calling driver_read_area(), which reads the pointer using
io_read!. After the pointer indicates new data is available, the CPU directly
reads the message payload without any intervening memory barrier:

drivers/gpu/nova-core/gsp/cmdq.rs:driver_read_area() {
    ...
        let tx = self.gsp_write_ptr();
        let rx = self.cpu_read_ptr();

        // Pointer to the first entry of the GSP message queue.
        let data = ptr::project!(self.0.as_ptr(), .gspq.msgq.data[build: 0]);

        let (tail_end, wrap_end) = if rx <= tx {
    ...
}

drivers/gpu/nova-core/gsp/cmdq.rs:wait_for_msg() {
    ...
        )
        .map(|(slice_1, slice_2)| (slice_1.as_flattened(), slice_2.as_flattened()))?;

        // Extract the GspMsgElement.
        let (header, slice_1) = GspMsgElement::from_bytes_prefix(slice_1).ok_or(EIO)?;
    ...
}

On weakly-ordered architectures, can the CPU speculatively execute the payload
data reads from the coherent DMA buffer before the read of the updated write
pointer has completed? Does this require a read-to-read DMA barrier (e.g.,
dma_mb(Read)) after reading the write pointer and before accessing the
payload?

[Severity: High]
This is also a pre-existing issue, but since the patch removes a CPU-centric
fence above, I noticed that advance_cpu_read_ptr() still uses one where a DMA
barrier might be required:

drivers/gpu/nova-core/gsp/cmdq.rs:advance_cpu_read_ptr() {
    ...
        let rptr = MsgqRxHeader::read_ptr(rx).wrapping_add(elem_count) % MSGQ_NUM_PAGES;

        // Ensure read pointer is properly ordered.
        fence(Ordering::SeqCst);

        MsgqRxHeader::set_read_ptr(rx, rptr)
    ...
}

In Rust, fence(Ordering::SeqCst) only provides an SMP-domain barrier. Since
the queue is in coherent DMA memory shared with a device, could the GSP
observe the advanced read pointer and overwrite the message payload while the
CPU is still reading it?

Should this use an Outer Shareable DMA barrier (like dma_mb(Full)) instead?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260819-rust-barrier-v3-0-d5b7bd7e6624@garyguo.net?part=1