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Thu, 20 Aug 2026 00:06:03 -0500 Received: from JesseDEV.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.45 via Frontend Transport; Thu, 20 Aug 2026 00:06:02 -0500 From: Jesse Zhang To: CC: , Christian Koenig , Jesse Zhang Subject: [PATCH v3 2/3] drm/amdgpu/mes_userqueue: add MODIFY support for SDMA user queues Date: Thu, 20 Aug 2026 13:05:36 +0800 Message-ID: <20260820050600.1249902-2-Jesse.Zhang@amd.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20260820050600.1249902-1-Jesse.Zhang@amd.com> References: <20260820050600.1249902-1-Jesse.Zhang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE1C:EE_|DM6PR12MB4281:EE_ X-MS-Office365-Filtering-Correlation-Id: 30070b26-4589-47ae-0dcf-08defe78bc46 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|23010399003|82310400026|36860700016|56012099006|10067099003|22082099003|11063799006|18002099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uxWzXhTXpalC93DIBnKG2AcTcv0sHpnCgjLpbUsktJ8QrNgWjq+UKmT9tUm9MUBY82mklybisPvR6z8T4Gjv1We1vFg/h/vB5QtpNE+WjPRtTo7s8UMAvMIXguLg6YW3Iyw1e1vUZjFEMJOGNP/+t0dCt+Hlc92iriv6YDSCyoBdjO6RwGnd7Wb2HjVIgCjFyff7u+cM09ia9wGyaS6DBXJnboCknUgMzlMtPAI8vtBI897c5OfxwbSVctAPajlvVxb3pThr3wNn693005AQ+ty2B/qhq3mxZLRWv2pfnzrcB4yN4biUEZaYuDVLifHcgbmN72OvI+8aLB4ao+DGfYs4mDwSI1a0jFZPgufKy+mk5NbwNde/NLkK337MeidlFjayFDvjEA01DleGI7ErT76Kbd5XmSDiNdYy8TgLZXrejqdsDYRZiTrkfTBuEcGo X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Aug 2026 05:06:04.0349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 30070b26-4589-47ae-0dcf-08defe78bc46 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4281 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Add the SDMA case to the mqd_update dispatcher so an SDMA user queue can be updated at runtime; until now it was rejected with -EINVAL. mes_userq_sdma_mqd_update() reads a drm_amdgpu_userq_mqd_sdma_gfx11 from user space, refreshes the queue props (csa address, queue size and ring base) and re-inits the MQD, mirroring the compute path. This aligns KGD user queues with KFD, which already supports updating SDMA queues via update_mqd_sdma. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 82bb4369451e..4f6d92031838 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -681,6 +681,36 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, return r; } +static int mes_userq_sdma_mqd_update(struct amdgpu_usermode_queue *queue, + struct drm_amdgpu_userq_in *args_in) +{ + int retval = 0; + struct amdgpu_device *adev = queue->userq_mgr->adev; + struct amdgpu_mqd_prop *userq_props = queue->userq_prop; + struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; + struct drm_amdgpu_userq_mqd_sdma_gfx11 *sdma_mqd_v11; + + if (args_in->mqd_size != sizeof(*sdma_mqd_v11)) { + DRM_ERROR("Invalid SDMA IP MQD size\n"); + return -EINVAL; + } + + sdma_mqd_v11 = memdup_user(u64_to_user_ptr(args_in->mqd), args_in->mqd_size); + if (IS_ERR(sdma_mqd_v11)) { + DRM_ERROR("Failed to read user MQD\n"); + return -ENOMEM; + } + + userq_props->csa_addr = sdma_mqd_v11->csa_va; + userq_props->queue_size = args_in->queue_size; + userq_props->hqd_base_gpu_addr = args_in->queue_va; + + retval = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props); + + kfree(sdma_mqd_v11); + return retval; +} + static int mes_userq_compute_mqd_update(struct amdgpu_usermode_queue *queue, struct drm_amdgpu_userq_in *args_in) { @@ -723,6 +753,8 @@ static int mes_userq_mqd_update(struct amdgpu_usermode_queue *queue, struct drm_ switch (queue->queue_type) { case AMDGPU_HW_IP_COMPUTE: return mes_userq_compute_mqd_update(queue, args_in); + case AMDGPU_HW_IP_DMA: + return mes_userq_sdma_mqd_update(queue, args_in); default: return -EINVAL; } -- 2.49.0