From: Jamin Lin <jamin_lin@aspeedtech.com>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Kane Chen" <kane_chen@aspeedtech.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Fabiano Rosas" <farosas@suse.de>,
"Laurent Vivier" <lvivier@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>
Subject: [PATCH v2 0/4] Add ASPEED ACRY RSA model for the AST2600
Date: Thu, 20 Aug 2026 08:12:07 +0000 [thread overview]
Message-ID: <20260820081206.3353463-1-jamin_lin@aspeedtech.com> (raw)
This series adds a model of the ASPEED ACRY engine found on the AST2600
SoC, wires it into the SoC, and adds a qtest.
The ACRY engine performs RSA modular exponentiation (c = m^e mod n). It
DMAs the operands (data, exponent, and modulus) from guest DRAM and writes
the result to a dedicated 64 KiB SRAM region.
Guest firmware uses the engine for RSA signature verification during boot.
Without a model, the guest starts the engine and waits indefinitely for a
completion interrupt, causing the boot to hang.
The model uses QEMU's generic akcipher API to perform raw (unpadded) RSA.
Raw RSA is currently supported only by the libgcrypt backend, which can be
enabled alongside gnutls with -Dgcrypt=enabled, so a build does not have to
choose between the two. When raw RSA is unavailable, the engine still
completes and raises its interrupt, but returns an all-zero result. This
allows the guest's signature verification to fail cleanly instead of
hanging. The qtest is skipped when the selected crypto backend does not
support raw RSA.
Although the hardware documentation describes both RSA and ECDSA support,
ECDSA is known to be broken on this hardware and is therefore not modeled.
v1:
1. Add ASPEED ACRY RSA model for the AST2600
2. Add qtest for AST2600 ASPEED ACRY RSA model
v2:
1. squash "Add the ACRY model to AspeedSoCState" into "Wire up the ACRY
model"
2. wrap the ACRY SRAM in a container mapped at offset 0 so the device
addresses it by relative offset (drop the "sram-base" property)
3. build the scattered SRAM byte offsets on the fly instead of caching
them in per-instance lookup tables
4. write the result with address_space_stl_le() and check the MemTxResult
Jamin Lin (4):
hw/misc/aspeed_acry: Add ASPEED ACRY model
hw/arm/aspeed_ast2600: Introduce the ACRY SRAM
hw/arm/aspeed_ast2600: Wire up the ACRY model
tests/qtest/aspeed-acry-test: Add RSA ModExp tests
include/hw/arm/aspeed_soc.h | 4 +
include/hw/misc/aspeed_acry.h | 39 +++
hw/arm/aspeed_ast2600.c | 34 +++
hw/misc/aspeed_acry.c | 455 +++++++++++++++++++++++++++++++++
tests/qtest/aspeed-acry-test.c | 395 ++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
hw/misc/trace-events | 6 +
tests/qtest/meson.build | 5 +-
8 files changed, 938 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/aspeed_acry.h
create mode 100644 hw/misc/aspeed_acry.c
create mode 100644 tests/qtest/aspeed-acry-test.c
--
2.53.0
next reply other threads:[~2026-08-20 8:12 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-20 8:12 Jamin Lin [this message]
2026-08-20 8:12 ` [PATCH v2 1/4] hw/misc/aspeed_acry: Add ASPEED ACRY model Jamin Lin
2026-08-20 8:12 ` [PATCH v2 2/4] hw/arm/aspeed_ast2600: Introduce the ACRY SRAM Jamin Lin
2026-08-20 13:02 ` Cédric Le Goater
2026-08-20 8:12 ` [PATCH v2 3/4] hw/arm/aspeed_ast2600: Wire up the ACRY model Jamin Lin
2026-08-20 13:03 ` Cédric Le Goater
2026-08-20 8:12 ` [PATCH v2 4/4] tests/qtest/aspeed-acry-test: Add RSA ModExp tests Jamin Lin
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