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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b3c556a3sm23707225e9.3.2026.08.20.03.48.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 20 Aug 2026 03:48:44 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Paolo Bonzini , Peter Maydell , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Subject: [RFC PATCH 10/13] target/riscv: Constify CPURISCVState for various cpu_*() getters Date: Thu, 20 Aug 2026 12:47:26 +0200 Message-ID: <20260820104730.25462-11-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260820104730.25462-1-philmd@oss.qualcomm.com> References: <20260820104730.25462-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: Cxuc_iMI5aKgwkVk5YxGbJN-lLyblngV X-Authority-Analysis: v=2.4 cv=V8BNF+ni c=1 sm=1 tr=0 ts=6a86db8e cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=W-temX7IfkLqO7pPVx4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIwMDA3OSBTYWx0ZWRfX0qOYuiucsMOI 213h2wvfTtdJZM142pKXQUoofdl16cTNHQ8ARddp6jsrs4A4esxaOaL7hlo8E2YJJdMIhRsyqIB Hgs4u3LPBhpIMy1DzhJgXhYISfkiwwEC/aNRQvK42nbIaPfb8WfVD1WPcTD5B+CQJoJraKOTSnI fU/5mM6Z9oSyl+n1pnaLwyElIWTjeLQMIMs1X4PBlWdtVJH4ng0rzRoUKN4GL26204G0Y+X4smY dLV7KLvQVFv2jRh28pUVR/0qiXn6P8pDkTiKtxTv6lpayC1KFI/TlXGZ/0euF9qrsi2JQfGISHJ mhf816fj1Ky/vujQBNdmwzWR/4ymFtgrcUjkj/Us9WASz7Z7sbY3vxhVUMR9XhXaE2SK/f+adaA vMtAaFoSReezrQtEdnDICYleeDPfnFSZn4bQod70XlEWD9ifgMe/YzRAab1wgXam189Wt7wiFv8 Xti6LBxFx+3bWC/VMIQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODIwMDA3OSBTYWx0ZWRfXx71rl0Cgq3tb wv++y5faXUiQdRyuoxArE86wHMRu6md1mx+eT9PbpKTwLwK7kyCPN0MuKZ1lb2WI/KhzEJCwWvH p/GPt/OPrvGtBLJI1bb6gC5uptRko0g= X-Proofpoint-GUID: Cxuc_iMI5aKgwkVk5YxGbJN-lLyblngV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-19_06,2026-08-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 bulkscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608200079 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the const qualifier to CPURISCVState when the argument is accessed without modification. Note we have to use the recently introduced env_archcpu_const() helper in riscv_cpu_cfg(). Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.h | 12 ++++++------ target/riscv/cpu.c | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2333dcecd8a..9fd9ba54147 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -637,10 +637,10 @@ int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); uint8_t riscv_cpu_default_priority(int irq); uint64_t riscv_cpu_all_pending(const CPURISCVState *env); -int riscv_cpu_mirq_pending(CPURISCVState *env); -int riscv_cpu_sirq_pending(CPURISCVState *env); -int riscv_cpu_vsirq_pending(CPURISCVState *env); -int riscv_cpu_pending_to_irq(CPURISCVState *env, +int riscv_cpu_mirq_pending(const CPURISCVState *env); +int riscv_cpu_sirq_pending(const CPURISCVState *env); +int riscv_cpu_vsirq_pending(const CPURISCVState *env); +int riscv_cpu_pending_to_irq(const CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, const uint8_t *iprio); @@ -753,9 +753,9 @@ static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env) #endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) -static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) +static inline const RISCVCPUConfig *riscv_cpu_cfg(const CPURISCVState *env) { - return &env_archcpu(env)->cfg; + return &env_archcpu_const(env)->cfg; } #if !defined(CONFIG_USER_ONLY) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a344daf62f8..ab2868dc1e2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -864,7 +864,7 @@ uint8_t riscv_cpu_default_priority(int irq) return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; }; -int riscv_cpu_pending_to_irq(CPURISCVState *env, +int riscv_cpu_pending_to_irq(const CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, const uint8_t *iprio) { @@ -917,7 +917,7 @@ uint64_t riscv_cpu_all_pending(const CPURISCVState *env) return (env->mip | vsgein | vstip) & env->mie; } -int riscv_cpu_mirq_pending(CPURISCVState *env) +int riscv_cpu_mirq_pending(const CPURISCVState *env) { uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); @@ -926,7 +926,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env) irqs, env->miprio); } -int riscv_cpu_sirq_pending(CPURISCVState *env) +int riscv_cpu_sirq_pending(const CPURISCVState *env) { uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & ~env->hideleg; uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie; @@ -935,7 +935,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env) irqs | irqs_f, env->siprio); } -int riscv_cpu_vsirq_pending(CPURISCVState *env) +int riscv_cpu_vsirq_pending(const CPURISCVState *env) { uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & env->hideleg; uint64_t irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie; -- 2.53.0