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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499a9e784b3sm117761165e9.3.2026.08.20.03.47.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 20 Aug 2026 03:47:54 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Paolo Bonzini , Peter Maydell , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Song Gao <17746591750@163.com>, Bibo Mao , Xianglai Li Subject: [PATCH 03/13] target/loongarch: Constify CPULoongArchState for various cpu_*() getters Date: Thu, 20 Aug 2026 12:47:19 +0200 Message-ID: <20260820104730.25462-4-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260820104730.25462-1-philmd@oss.qualcomm.com> References: <20260820104730.25462-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: MpMGTb0qbcbIbXN0DDeKggZVfZ2Y4p4y X-Proofpoint-Spam-Info: AW1haW4tMjYwODIwMDA3OSBTYWx0ZWRfX0pXin+RfmYGF v6aDdZjX3ZCpz8QEfKA47TlJmB1rKeeRzjWIihh8Ivp8ZU0iyEwSr0bYN2idfWP661bIMUAsvrQ roGf8E/sTtc2JjBOH1dQ1G8qfl9HapI= X-Authority-Analysis: v=2.4 cv=T/O8ifKQ c=1 sm=1 tr=0 ts=6a86db5b cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=cEYDorbIuKFc_Ye4BekA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIwMDA3OSBTYWx0ZWRfX03Tk4AArW/7y /tI28AwIKio/IYiW2Q14V7O6XBQC1r97s5RXQ1I9vi8OghQmvDR4UJE22ogISKqsrVjetSNVSna E7skNX/ZewXnvYbhBCJTZFQWAZySEC6Ec+NcGEBEQqdOk6wGkQ2S3KnUidUHX8NmXEdQyjKSVmu tT+tAM1CjEbxJ35aSyiLtdH+7xP3m/SQjbIEBnGXAGns/ZZpxrX6c62UU4ZHKG3cJNoeJIiZES2 snKXswC9ioxwp23GhXcve84aq/c57RbPQlzqZiN359kZI9CcVnYr5meMhkl5S7fzoG/v0q8r4DF /CUMvbiA233z+9svhIP29dMlRWuCuiKV8TZLPNky9kMVTzNIQypxg3IeScxw6HQWPtvYniRNlvl Y7gQjuC44XH9LMZWgC4Oz+5vo8da6qPtm/TEOAwLbXYNfjT1BPqBNDIo0TNlDs3irrg7he6MYIC MTsfsPHmeo7r7Lpw+Dw== X-Proofpoint-ORIG-GUID: MpMGTb0qbcbIbXN0DDeKggZVfZ2Y4p4y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-19_06,2026-08-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 bulkscore=0 spamscore=0 adultscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608200079 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Add the const qualifier to CPULoongArchStatCPUMIPSStatee when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daudé --- target/loongarch/cpu.h | 6 +++--- target/loongarch/internals.h | 2 +- target/loongarch/cpu.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index ad30c73167e..494744788b8 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -485,7 +485,7 @@ struct LoongArchCPUClass { #define MMU_USER_IDX MMU_PLV_USER #define MMU_DA_IDX 4 -static inline CPUSysState *env_sys(CPULoongArchState *env) +static inline CPUSysState *env_sys(const CPULoongArchState *env) { return env->sys_state; } @@ -495,12 +495,12 @@ static inline void set_sys_state(CPULoongArchState *env, CPUSysState *sys) env->sys_state = sys; } -static inline bool is_la64(CPULoongArchState *env) +static inline bool is_la64(const CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64; } -static inline bool is_va32(CPULoongArchState *env) +static inline bool is_va32(const CPULoongArchState *env) { /* VA32 if !LA64 or VA32L[1-3] */ bool va32 = !is_la64(env); diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index e01dbed40f6..6a733e6c3a5 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -39,7 +39,7 @@ uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu); void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu, uint64_t value); bool loongarch_cpu_has_work(CPUState *cs); -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env); +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env); #endif /* !CONFIG_USER_ONLY */ uint64_t read_fcc(CPULoongArchState *env); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 8cd5bc18a3c..82ec35e081f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -82,7 +82,7 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level) } /* Check if there is pending and not masked out interrupt */ -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env) { uint32_t pending; uint32_t status; -- 2.53.0