From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: stable@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
patches@lists.linux.dev, Dillon Varone <dillon.varone@amd.com>,
Clay King <clayking@amd.com>, James Lin <pinglei.lin@amd.com>,
Daniel Wheeler <daniel.wheeler@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Sasha Levin <sashal@kernel.org>
Subject: [PATCH 7.1 152/228] drm/amd/display: Fix warnings
Date: Thu, 20 Aug 2026 16:54:54 +0200 [thread overview]
Message-ID: <20260820145249.260724528@linuxfoundation.org> (raw)
In-Reply-To: <20260820145244.450574346@linuxfoundation.org>
7.1-stable review patch. If anyone has any objections, please let me know.
------------------
From: Clay King <clayking@amd.com>
[ Upstream commit c3fb1fb9e65fa6a108b4d19c61bdcb47fd4fe180 ]
[Why & How]
Fix various warnings related to unsigned/signed mismatches
- Consistently use the same signedness for a given value
- Explcitly cast between types when needed
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Clay King <clayking@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stable-dep-of: 93c8fe6d5603 ("drm/amd/display: guard against overflow in HDCP message dump")
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 6
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h | 2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 8
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h | 2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h | 4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c | 4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h | 2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 2
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c | 2
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 18
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 4
drivers/gpu/drm/amd/display/dc/dc.h | 68 -
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 2
drivers/gpu/drm/amd/display/dc/dc_stream.h | 4
drivers/gpu/drm/amd/display/dc/dc_types.h | 2
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c | 2
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c | 2
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 4
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 28
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 342 ++++----
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 408 +++++-----
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c | 400 ++++-----
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 8
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h | 8
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 12
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c | 2
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 2
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c | 4
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 8
drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c | 8
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c | 10
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c | 4
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h | 2
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 6
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 2
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2
drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h | 2
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 2
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 4
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 8
drivers/gpu/drm/amd/display/dc/inc/link_service.h | 2
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h | 72 -
drivers/gpu/drm/amd/display/dc/link/link_detection.c | 2
drivers/gpu/drm/amd/display/dc/link/link_detection.h | 2
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c | 8
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c | 2
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c | 6
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c | 2
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h | 2
drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 2
drivers/gpu/drm/amd/display/include/fixed31_32.h | 6
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c | 2
59 files changed, 769 insertions(+), 767 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -88,7 +88,7 @@ static const struct state_dependent_cloc
/* ClocksStatePerformance */
{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
-int dentist_get_divider_from_did(int did)
+unsigned int dentist_get_divider_from_did(unsigned int did)
{
if (did < DENTIST_BASE_DID_1)
did = DENTIST_BASE_DID_1;
@@ -155,8 +155,8 @@ static int dce60_get_dp_ref_freq_khz(str
int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
- int dprefclk_wdivider;
- int dprefclk_src_sel;
+ uint32_t dprefclk_wdivider;
+ uint32_t dprefclk_src_sel;
int dp_ref_clk_khz;
int target_div;
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
@@ -54,6 +54,6 @@ int dce_set_clock(
void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr);
-int dentist_get_divider_from_did(int did);
+unsigned int dentist_get_divider_from_did(unsigned int did);
#endif /* _DCE_CLK_MGR_H_ */
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -427,8 +427,8 @@ void dcn2_read_clocks_from_hw_dentist(st
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint32_t dispclk_wdivider;
uint32_t dppclk_wdivider;
- int disp_divider;
- int dpp_divider;
+ unsigned int disp_divider;
+ unsigned int dpp_divider;
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider);
@@ -531,8 +531,8 @@ void dcn20_clk_mgr_construct(
struct pp_smu_funcs *pp_smu,
struct dccg *dccg)
{
- int dprefclk_did;
- int target_div;
+ unsigned int dprefclk_did;
+ unsigned int target_div;
uint32_t pll_req_reg;
struct fixed31_32 pll_req;
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
@@ -123,12 +123,12 @@ bool dcn30_smu_test_message(struct clk_m
return false;
}
-bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
+bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version)
{
smu_print("SMU Get SMU version\n");
if (dcn30_smu_send_msg_with_param(clk_mgr,
- DALSMC_MSG_GetSmuVersion, 0, version)) {
+ DALSMC_MSG_GetSmuVersion, 0, (uint32_t *)version)) {
smu_print("SMU version: %d\n", *version);
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
@@ -31,7 +31,7 @@
struct clk_mgr_internal;
bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
-bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
+bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version);
bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -482,7 +482,7 @@ static int dcn32_get_dispclk_from_dentis
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint32_t dispclk_wdivider;
- int disp_divider;
+ unsigned int disp_divider;
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -1487,7 +1487,7 @@ static int dcn401_get_dispclk_from_denti
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint32_t dispclk_wdivider;
- int disp_divider;
+ unsigned int disp_divider;
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
@@ -17,14 +17,14 @@ union dcn401_clk_mgr_block_sequence_para
uint32_t ppclk;
uint16_t freq_mhz;
/* outputs */
- uint32_t *response;
+ int *response;
} update_hardmin_params;
struct {
/* inputs */
uint32_t ppclk;
int freq_khz;
/* outputs */
- uint32_t *response;
+ int *response;
} update_hardmin_optimized_params;
struct {
/* inputs */
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
@@ -143,12 +143,12 @@ static bool dcn401_smu_send_msg_with_par
return false;
}
-bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
+bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version)
{
smu_print("SMU Get SMU version\n");
if (dcn401_smu_send_msg_with_param(clk_mgr,
- DALSMC_MSG_GetSmuVersion, 0, version)) {
+ DALSMC_MSG_GetSmuVersion, 0, (uint32_t *)version)) {
smu_print("SMU version: %d\n", *version);
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
@@ -10,7 +10,7 @@
struct clk_mgr_internal;
-bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
+bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version);
bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -870,7 +870,7 @@ int dcn42_get_dispclk_from_dentist(struc
(void)clk_mgr_base;
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint32_t dispclk_wdivider;
- int disp_divider;
+ unsigned int disp_divider;
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -6710,7 +6710,7 @@ bool dc_can_clear_cursor_limit(const str
return false;
}
-void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst,
+void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst,
struct dc_underflow_debug_data *out_data)
{
struct timing_generator *tg = NULL;
@@ -6728,7 +6728,7 @@ void dc_get_underflow_debug_data_for_otg
dc->hwss.get_underflow_debug_data(dc, tg, out_data);
}
-void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst,
+void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst,
struct power_features *out_data)
{
(void)primary_otg_inst;
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
@@ -282,7 +282,7 @@ unsigned int dc_dp_trace_get_link_loss_c
struct dc_sink *dc_link_add_remote_sink(
struct dc_link *link,
const uint8_t *edid,
- int len,
+ unsigned int len,
struct dc_sink_init_data *init_data)
{
return link->dc->link_srv->add_remote_sink(link, edid, len, init_data);
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -982,7 +982,7 @@ static struct rect calculate_mpc_slice_i
}
static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx,
- int *base_offset, int *dpp_offset)
+ unsigned int *base_offset, unsigned int *dpp_offset)
{
struct dc *dc = pipe_ctx->stream->ctx->dc;
*base_offset = 0;
@@ -1004,7 +1004,7 @@ static void calculate_adjust_recout_for_
static void reverse_adjust_recout_for_visual_confirm(struct rect *recout,
struct pipe_ctx *pipe_ctx)
{
- int dpp_offset, base_offset;
+ unsigned int dpp_offset, base_offset;
calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,
&dpp_offset);
@@ -1015,7 +1015,7 @@ static void reverse_adjust_recout_for_vi
static void adjust_recout_for_visual_confirm(struct rect *recout,
struct pipe_ctx *pipe_ctx)
{
- int dpp_offset, base_offset;
+ unsigned int dpp_offset, base_offset;
calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,
&dpp_offset);
@@ -1692,7 +1692,7 @@ bool resource_can_pipe_disable_cursor(st
struct pipe_ctx *test_pipe, *split_pipe;
struct rect r1 = pipe_ctx->plane_res.scl_data.recout;
int r1_right, r1_bottom;
- int cur_layer = pipe_ctx->plane_state->layer_index;
+ unsigned int cur_layer = pipe_ctx->plane_state->layer_index;
reverse_adjust_recout_for_visual_confirm(&r1, pipe_ctx);
r1_right = r1.x + r1.width;
@@ -4102,9 +4102,9 @@ bool dc_resource_is_dsc_encoding_support
static bool planes_changed_for_existing_stream(struct dc_state *context,
struct dc_stream_state *stream,
const struct dc_validation_set set[],
- int set_count)
+ unsigned int set_count)
{
- int i, j;
+ unsigned int i, j;
struct dc_stream_status *stream_status = NULL;
for (i = 0; i < context->stream_count; i++) {
@@ -4140,10 +4140,10 @@ static bool add_all_planes_for_stream(
const struct dc *dc,
struct dc_stream_state *stream,
const struct dc_validation_set set[],
- int set_count,
+ unsigned int set_count,
struct dc_state *state)
{
- int i, j;
+ unsigned int i, j;
for (i = 0; i < set_count; i++)
if (set[i].stream == stream)
@@ -4181,7 +4181,7 @@ static bool add_all_planes_for_stream(
*/
enum dc_status dc_validate_with_context(struct dc *dc,
const struct dc_validation_set set[],
- int set_count,
+ unsigned int set_count,
struct dc_state *context,
enum dc_validate_mode validate_mode)
{
--- a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
@@ -34,9 +34,9 @@ void vm_helper_mark_vmid_used(struct vm_
vmids.vmid_usage[1] = 1 << pos;
}
-int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config)
+unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config)
{
- int num_vmids = 0;
+ unsigned int num_vmids = 0;
/* Call HWSS to setup HUBBUB for address config */
if (dc->hwss.init_sys_ctx) {
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -540,7 +540,7 @@ struct dc_config {
bool use_default_clock_table;
bool force_bios_enable_lttpr;
uint8_t force_bios_fixed_vs;
- int sdpif_request_limit_words_per_umc;
+ unsigned int sdpif_request_limit_words_per_umc;
bool dc_mode_clk_limit_support;
bool EnableMinDispClkODM;
bool enable_auto_dpm_test_logs;
@@ -944,20 +944,20 @@ struct dc_virtual_addr_space_config {
};
struct dc_bounding_box_overrides {
- int sr_exit_time_ns;
- int sr_enter_plus_exit_time_ns;
- int sr_exit_z8_time_ns;
- int sr_enter_plus_exit_z8_time_ns;
- int urgent_latency_ns;
- int percent_of_ideal_drambw;
- int dram_clock_change_latency_ns;
- int dummy_clock_change_latency_ns;
- int fclk_clock_change_latency_ns;
+ unsigned int sr_exit_time_ns;
+ unsigned int sr_enter_plus_exit_time_ns;
+ unsigned int sr_exit_z8_time_ns;
+ unsigned int sr_enter_plus_exit_z8_time_ns;
+ unsigned int urgent_latency_ns;
+ unsigned int percent_of_ideal_drambw;
+ unsigned int dram_clock_change_latency_ns;
+ unsigned int dummy_clock_change_latency_ns;
+ unsigned int fclk_clock_change_latency_ns;
/* This forces a hard min on the DCFCLK we use
* for DML. Unlike the debug option for forcing
* DCFCLK, this override affects watermark calculations
*/
- int min_dcfclk_mhz;
+ unsigned int min_dcfclk_mhz;
};
struct dc_qos_info {
@@ -989,7 +989,7 @@ struct link_service;
struct dc_debug_options {
bool disable_dsc;
enum visual_confirm visual_confirm;
- int visual_confirm_rect_height;
+ unsigned int visual_confirm_rect_height;
bool sanity_checks;
bool max_disp_clk;
@@ -1025,23 +1025,23 @@ struct dc_debug_options {
bool disable_io_clk_power_gate;
bool disable_mem_power_gate;
bool disable_dio_power_gate;
- int dsc_min_slice_height_override;
- int dsc_bpp_increment_div;
+ unsigned int dsc_min_slice_height_override;
+ unsigned int dsc_bpp_increment_div;
bool disable_pplib_wm_range;
enum wm_report_mode pplib_wm_report_mode;
unsigned int min_disp_clk_khz;
unsigned int min_dpp_clk_khz;
unsigned int min_dram_clk_khz;
- int sr_exit_time_dpm0_ns;
- int sr_enter_plus_exit_time_dpm0_ns;
- int sr_exit_time_ns;
- int sr_enter_plus_exit_time_ns;
- int sr_exit_z8_time_ns;
- int sr_enter_plus_exit_z8_time_ns;
- int urgent_latency_ns;
+ unsigned int sr_exit_time_dpm0_ns;
+ unsigned int sr_enter_plus_exit_time_dpm0_ns;
+ unsigned int sr_exit_time_ns;
+ unsigned int sr_enter_plus_exit_time_ns;
+ unsigned int sr_exit_z8_time_ns;
+ unsigned int sr_enter_plus_exit_z8_time_ns;
+ unsigned int urgent_latency_ns;
uint32_t underflow_assert_delay_us;
- int percent_of_ideal_drambw;
- int dram_clock_change_latency_ns;
+ unsigned int percent_of_ideal_drambw;
+ unsigned int dram_clock_change_latency_ns;
bool optimized_watermark;
int always_scale;
bool disable_pplib_clock_request;
@@ -1066,8 +1066,8 @@ struct dc_debug_options {
uint8_t seamless_boot_odm_combine;
uint8_t force_odm_combine_4to1; //bit vector based on otg inst
- int minimum_z8_residency_time;
- int minimum_z10_residency_time;
+ unsigned int minimum_z8_residency_time;
+ unsigned int minimum_z10_residency_time;
bool disable_z9_mpc;
unsigned int force_fclk_khz;
bool enable_tri_buf;
@@ -1116,7 +1116,7 @@ struct dc_debug_options {
uint8_t fec_enable_delay_in100us;
bool enable_driver_sequence_debug;
enum det_size crb_alloc_policy;
- int crb_alloc_policy_min_disp_count;
+ unsigned int crb_alloc_policy_min_disp_count;
bool disable_z10;
bool enable_z9_disable_interface;
bool psr_skip_crtc_disable;
@@ -1290,7 +1290,7 @@ void dc_hardware_init(struct dc *dc);
int dc_get_vmid_use_vector(struct dc *dc);
void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
/* Returns the number of vmids supported */
-int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
+unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
void dc_init_callbacks(struct dc *dc,
const struct dc_callback_init *init_params);
void dc_deinit_callbacks(struct dc *dc);
@@ -1515,7 +1515,7 @@ struct dc_plane_state {
bool visible;
bool flip_immediate;
bool horizontal_mirror;
- int layer_index;
+ unsigned int layer_index;
union surface_update_flags update_flags;
bool flip_int_enabled;
@@ -1545,7 +1545,7 @@ struct dc_plane_state {
struct dc_csc_transform cursor_csc_color_matrix;
bool adaptive_sharpness_en;
int adaptive_sharpness_policy;
- int sharpness_level;
+ unsigned int sharpness_level;
enum linear_light_scaling linear_light_scaling;
unsigned int sdr_white_level_nits;
struct cm_hist_control cm_hist_control;
@@ -1568,7 +1568,7 @@ struct dc_plane_info {
bool global_alpha;
int global_alpha_value;
bool input_csc_enabled;
- int layer_index;
+ unsigned int layer_index;
enum chroma_cositing cositing;
};
@@ -1976,7 +1976,7 @@ enum dc_status dc_validate_plane(struct
enum dc_status dc_validate_with_context(struct dc *dc,
const struct dc_validation_set set[],
- int set_count,
+ unsigned int set_count,
struct dc_state *context,
enum dc_validate_mode validate_mode);
@@ -2088,7 +2088,7 @@ struct dc_sink_init_data;
struct dc_sink *dc_link_add_remote_sink(
struct dc_link *dc_link,
const uint8_t *edid,
- int len,
+ unsigned int len,
struct dc_sink_init_data *init_data);
/* Remove remote sink from a link with dc_connection_mst_branch connection type.
@@ -2886,9 +2886,9 @@ bool dc_can_clear_cursor_limit(const str
* including OTG underflow status, current read positions, frame count, and per-HUBP debug data.
* The results are stored in the provided out_data structure for further analysis or logging.
*/
-void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data);
+void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data);
-void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, struct power_features *out_data);
+void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data);
/*
* Software state variables used to program register fields across the display pipeline
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -92,7 +92,7 @@ uint32_t dc_dsc_stream_bandwidth_in_kbps
uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(
const struct dc_crtc_timing *timing,
- const int num_slices_h,
+ const uint32_t num_slices_h,
const bool is_dp);
void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -179,8 +179,8 @@ struct luminance_data {
int luminance_millinits[LUMINANCE_DATA_TABLE_SIZE];
int flicker_criteria_milli_nits_GAMING;
int flicker_criteria_milli_nits_STATIC;
- int nominal_refresh_rate;
- int dm_max_decrease_from_nominal;
+ unsigned int nominal_refresh_rate;
+ unsigned int dm_max_decrease_from_nominal;
};
enum dc_drr_trigger_mode {
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -887,7 +887,7 @@ struct dsc_dec_dpcd_caps {
union dsc_slice_caps2 slice_caps2;
int32_t lb_bit_depth;
bool is_block_pred_supported;
- int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
+ uint32_t edp_max_bits_per_pixel; /* Valid only in eDP */
union dsc_color_formats color_formats;
union dsc_color_depth color_depth;
int32_t throughput_mode_0_mps; /* In MPs */
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
@@ -205,7 +205,7 @@ static bool update_cfg_data(
static bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
{
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
- int value;
+ uint32_t value;
if (enc->features.flags.bits.DP_IS_USB_C) {
REG_GET(RDPCSTX_PHY_CNTL6,
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
@@ -450,7 +450,7 @@ static uint8_t get_frontend_source(
unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
{
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
- int32_t value;
+ uint32_t value;
enum engine_id result;
REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1105,7 +1105,7 @@ static enum dcn_zstate_support_state de
}
static void dcn20_adjust_freesync_v_startup(
- const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start)
+ const struct dc_crtc_timing *dc_crtc_timing, unsigned int *vstartup_start)
{
struct dc_crtc_timing patched_crtc_timing;
uint32_t asic_blank_end = 0;
@@ -1253,7 +1253,7 @@ void dcn20_calculate_dlg_params(struct d
static void swizzle_to_dml_params(
enum swizzle_mode_values swizzle,
- unsigned int *sw_mode)
+ int *sw_mode)
{
switch (swizzle) {
case DC_SW_LINEAR:
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -296,7 +296,7 @@ static void CalculateWatermarksAndDRAMSp
double UrgentOutOfOrderReturn,
double ReturnBW,
bool GPUVMEnable,
- int dpte_group_bytes[],
+ unsigned int dpte_group_bytes[],
unsigned int MetaChunkSize,
double UrgentLatency,
double ExtraLatency,
@@ -307,7 +307,7 @@ static void CalculateWatermarksAndDRAMSp
double SRExitTime,
double SREnterPlusExitTime,
double DCFCLKDeepSleep,
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
bool DCCEnable[],
double DPPCLK[],
double SwathWidthSingleDPPY[],
@@ -346,7 +346,7 @@ static void CalculateDCFCLKDeepSleep(
double BytePerPixelDETC[],
double VRatio[],
double SwathWidthY[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double HRatio[],
double PixelClock[],
double PSCL_THROUGHPUT[],
@@ -390,7 +390,7 @@ static void CalculatePixelDeliveryTimes(
double VRatioPrefetchC[],
unsigned int swath_width_luma_ub[],
unsigned int swath_width_chroma_ub[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double HRatio[],
double PixelClock[],
double PSCL_THROUGHPUT[],
@@ -436,7 +436,7 @@ static void CalculateMetaAndPTETimes(
unsigned int meta_row_height[],
unsigned int meta_req_width[],
unsigned int meta_req_height[],
- int dpte_group_bytes[],
+ unsigned int dpte_group_bytes[],
unsigned int PTERequestSizeY[],
unsigned int PTERequestSizeC[],
unsigned int PixelPTEReqWidthY[],
@@ -477,8 +477,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
int HostVMMaxPageTableLevels,
@@ -5257,7 +5257,7 @@ static void CalculateWatermarksAndDRAMSp
double UrgentOutOfOrderReturn,
double ReturnBW,
bool GPUVMEnable,
- int dpte_group_bytes[],
+ unsigned int dpte_group_bytes[],
unsigned int MetaChunkSize,
double UrgentLatency,
double ExtraLatency,
@@ -5268,7 +5268,7 @@ static void CalculateWatermarksAndDRAMSp
double SRExitTime,
double SREnterPlusExitTime,
double DCFCLKDeepSleep,
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
bool DCCEnable[],
double DPPCLK[],
double SwathWidthSingleDPPY[],
@@ -5543,7 +5543,7 @@ static void CalculateDCFCLKDeepSleep(
double BytePerPixelDETC[],
double VRatio[],
double SwathWidthY[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double HRatio[],
double PixelClock[],
double PSCL_THROUGHPUT[],
@@ -5749,7 +5749,7 @@ static void CalculatePixelDeliveryTimes(
double VRatioPrefetchC[],
unsigned int swath_width_luma_ub[],
unsigned int swath_width_chroma_ub[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double HRatio[],
double PixelClock[],
double PSCL_THROUGHPUT[],
@@ -5870,7 +5870,7 @@ static void CalculateMetaAndPTETimes(
unsigned int meta_row_height[],
unsigned int meta_req_width[],
unsigned int meta_req_height[],
- int dpte_group_bytes[],
+ unsigned int dpte_group_bytes[],
unsigned int PTERequestSizeY[],
unsigned int PTERequestSizeC[],
unsigned int PixelPTEReqWidthY[],
@@ -6128,8 +6128,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
int HostVMMaxPageTableLevels,
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -285,8 +285,8 @@ static void CalculateWatermarksAndDRAMSp
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -327,7 +327,7 @@ static void CalculateUrgentBurstFactor(
static void UseMinimumDCFCLK(
struct display_mode_lib *mode_lib,
struct vba_vars_st *v,
- int MaxPrefetchMode,
+ unsigned int MaxPrefetchMode,
int ReorderingBytes);
static void CalculatePixelDeliveryTimes(
@@ -345,7 +345,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][2],
@@ -370,35 +370,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -421,18 +421,18 @@ static void CalculateVMGroupAndRequestTi
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -446,27 +446,27 @@ static void CalculateStutterEfficiency(
double ReturnBW,
double SRExitTime,
bool SynchronizedVBlank,
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double DCCRateLuma[],
double DCCRateChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -486,32 +486,32 @@ static void CalculateSwathAndDETConfigur
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
@@ -528,22 +528,22 @@ static void CalculateSwathWidth(
unsigned int SurfaceHeightY[],
unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
unsigned int swath_width_luma_ub[],
unsigned int swath_width_chroma_ub[]);
static double CalculateExtraLatency(
@@ -558,8 +558,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
double HostVMMinPageSize,
@@ -573,8 +573,8 @@ static double CalculateExtraLatencyBytes
bool GPUVMEnable,
bool HostVMEnable,
unsigned int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
double HostVMMinPageSize,
@@ -2888,18 +2888,18 @@ static void DisplayPipeConfiguration(str
// Display Pipe Configuration
double BytePerPixDETY[DC__NUM_DPP__MAX] = { 0 };
double BytePerPixDETC[DC__NUM_DPP__MAX] = { 0 };
- int BytePerPixY[DC__NUM_DPP__MAX] = { 0 };
- int BytePerPixC[DC__NUM_DPP__MAX] = { 0 };
- int Read256BytesBlockHeightY[DC__NUM_DPP__MAX] = { 0 };
- int Read256BytesBlockHeightC[DC__NUM_DPP__MAX] = { 0 };
- int Read256BytesBlockWidthY[DC__NUM_DPP__MAX] = { 0 };
- int Read256BytesBlockWidthC[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int BytePerPixY[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int BytePerPixC[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX] = { 0 };
double dummy1[DC__NUM_DPP__MAX] = { 0 };
double dummy2[DC__NUM_DPP__MAX] = { 0 };
double dummy3[DC__NUM_DPP__MAX] = { 0 };
double dummy4[DC__NUM_DPP__MAX] = { 0 };
- int dummy5[DC__NUM_DPP__MAX] = { 0 };
- int dummy6[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int dummy5[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int dummy6[DC__NUM_DPP__MAX] = { 0 };
bool dummy7[DC__NUM_DPP__MAX] = { 0 };
bool dummysinglestring = 0;
unsigned int k;
@@ -3381,7 +3381,7 @@ static double TruncToValidBPP(
void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
{
struct vba_vars_st *v = &mode_lib->vba;
- int MinPrefetchMode, MaxPrefetchMode;
+ unsigned int MinPrefetchMode, MaxPrefetchMode;
int idx, start_state;
unsigned int i, j, k, m;
bool EnoughWritebackUnits = true;
@@ -4550,7 +4550,7 @@ void dml30_ModeSupportAndSystemConfigura
for (i = start_state; i < mode_lib->soc.num_states; ++i) {
for (j = 0; j <= 1; ++j) {
- int NextPrefetchModeState = MinPrefetchMode;
+ unsigned int NextPrefetchModeState = MinPrefetchMode;
v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j];
@@ -5153,8 +5153,8 @@ static void CalculateWatermarksAndDRAMSp
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -5306,7 +5306,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][2],
@@ -5411,35 +5411,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -5584,18 +5584,18 @@ static void CalculateVMGroupAndRequestTi
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -5700,27 +5700,27 @@ static void CalculateStutterEfficiency(
double ReturnBW,
double SRExitTime,
bool SynchronizedVBlank,
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double DCCRateLuma[],
double DCCRateChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -5854,42 +5854,42 @@ static void CalculateSwathAndDETConfigur
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
bool *ViewportSizeSupport)
{
(void)HRatioChroma;
- int MaximumSwathHeightY[DC__NUM_DPP__MAX] = { 0 };
- int MaximumSwathHeightC[DC__NUM_DPP__MAX] = { 0 };
- int MinimumSwathHeightY = 0;
- int MinimumSwathHeightC = 0;
+ unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int MinimumSwathHeightY = 0;
+ unsigned int MinimumSwathHeightC = 0;
long RoundedUpMaxSwathSizeBytesY = 0;
long RoundedUpMaxSwathSizeBytesC = 0;
long RoundedUpMinSwathSizeBytesY = 0;
@@ -6049,22 +6049,22 @@ static void CalculateSwathWidth(
unsigned int SurfaceHeightY[],
unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
unsigned int swath_width_luma_ub[],
unsigned int swath_width_chroma_ub[])
{
@@ -6157,8 +6157,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
double HostVMMinPageSize,
@@ -6193,8 +6193,8 @@ static double CalculateExtraLatencyBytes
bool GPUVMEnable,
bool HostVMEnable,
unsigned int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
double HostVMMinPageSize,
@@ -6251,7 +6251,7 @@ static double CalculateUrgentLatency(
static noinline_for_stack void UseMinimumDCFCLK(
struct display_mode_lib *mode_lib,
struct vba_vars_st *v,
- int MaxPrefetchMode,
+ unsigned int MaxPrefetchMode,
int ReorderingBytes)
{
double NormalEfficiency = 0;
@@ -6276,7 +6276,7 @@ static noinline_for_stack void UseMinimu
double ExtraLatencyBytes = 0;
double ExtraLatencyCycles = 0;
double DCFCLKRequiredForPeakBandwidth = 0;
- int NoOfDPPState[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int NoOfDPPState[DC__NUM_DPP__MAX] = { 0 };
double MinimumTvmPlus2Tr0 = 0;
TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -157,7 +157,7 @@ static bool CalculatePrefetchSchedule(
double *Tdmdl_vm,
double *Tdmdl,
double *TSetup,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix);
static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
@@ -218,19 +218,19 @@ static unsigned int CalculateVMAndRowByt
unsigned int *MetaRowByte,
unsigned int *PixelPTEBytesPerRow,
bool *PTEBufferSizeNotExceeded,
- int *dpte_row_width_ub,
+ unsigned int *dpte_row_width_ub,
unsigned int *dpte_row_height,
unsigned int *MetaRequestWidth,
unsigned int *MetaRequestHeight,
unsigned int *meta_row_width,
unsigned int *meta_row_height,
- int *vm_group_bytes,
+ unsigned int *vm_group_bytes,
unsigned int *dpte_group_bytes,
unsigned int *PixelPTEReqWidth,
unsigned int *PixelPTEReqHeight,
unsigned int *PTERequestSize,
- int *DPDE0BytesFrame,
- int *MetaPTEBytesFrame);
+ unsigned int *DPDE0BytesFrame,
+ unsigned int *MetaPTEBytesFrame);
static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime);
static void CalculateRowBandwidth(
bool GPUVMEnable,
@@ -285,7 +285,7 @@ static void CalculateVupdateAndDynamicMe
double *Tdmbf,
double *Tdmec,
double *Tdmsks,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix);
@@ -318,8 +318,8 @@ static void CalculateWatermarksAndDRAMSp
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -377,7 +377,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
@@ -402,35 +402,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -453,18 +453,18 @@ static void CalculateVMGroupAndRequestTi
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -492,29 +492,29 @@ static void CalculateStutterEfficiency(
bool ProgressiveToInterlaceUnitInOPP,
bool Interlace[],
double MinTTUVBlank[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double NetDCCRateLuma[],
double NetDCCRateChroma[],
double DCCFractionOfZeroSizeRequestsLuma[],
double DCCFractionOfZeroSizeRequestsChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -539,32 +539,32 @@ static void CalculateSwathAndDETConfigur
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
@@ -574,31 +574,31 @@ static void CalculateSwathWidth(
int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
- int HActive[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[]);
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[]);
static double CalculateExtraLatency(
int RoundTripPingLatencyCycles,
@@ -612,8 +612,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels);
@@ -627,8 +627,8 @@ static double CalculateExtraLatencyBytes
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels);
@@ -652,7 +652,7 @@ static void CalculateUnboundedRequestAnd
int CompressedBufferSegmentSizeInkByteFinal,
enum output_encoder_class *Output,
bool *UnboundedRequestEnabled,
- int *CompressedBufferSizeInkByte);
+ unsigned int *CompressedBufferSizeInkByte);
static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output);
@@ -869,7 +869,7 @@ static bool CalculatePrefetchSchedule(
double *Tdmdl_vm,
double *Tdmdl,
double *TSetup,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
@@ -1818,19 +1818,19 @@ static unsigned int CalculateVMAndRowByt
unsigned int *MetaRowByte,
unsigned int *PixelPTEBytesPerRow,
bool *PTEBufferSizeNotExceeded,
- int *dpte_row_width_ub,
+ unsigned int *dpte_row_width_ub,
unsigned int *dpte_row_height,
unsigned int *MetaRequestWidth,
unsigned int *MetaRequestHeight,
unsigned int *meta_row_width,
unsigned int *meta_row_height,
- int *vm_group_bytes,
+ unsigned int *vm_group_bytes,
unsigned int *dpte_group_bytes,
unsigned int *PixelPTEReqWidth,
unsigned int *PixelPTEReqHeight,
unsigned int *PTERequestSize,
- int *DPDE0BytesFrame,
- int *MetaPTEBytesFrame)
+ unsigned int *DPDE0BytesFrame,
+ unsigned int *MetaPTEBytesFrame)
{
(void)SourcePixelFormat;
struct vba_vars_st *v = &mode_lib->vba;
@@ -3278,18 +3278,18 @@ static void DisplayPipeConfiguration(str
// Display Pipe Configuration
double BytePerPixDETY[DC__NUM_DPP__MAX];
double BytePerPixDETC[DC__NUM_DPP__MAX];
- int BytePerPixY[DC__NUM_DPP__MAX];
- int BytePerPixC[DC__NUM_DPP__MAX];
- int Read256BytesBlockHeightY[DC__NUM_DPP__MAX];
- int Read256BytesBlockHeightC[DC__NUM_DPP__MAX];
- int Read256BytesBlockWidthY[DC__NUM_DPP__MAX];
- int Read256BytesBlockWidthC[DC__NUM_DPP__MAX];
+ unsigned int BytePerPixY[DC__NUM_DPP__MAX];
+ unsigned int BytePerPixC[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX];
double dummy1[DC__NUM_DPP__MAX];
double dummy2[DC__NUM_DPP__MAX];
double dummy3[DC__NUM_DPP__MAX];
double dummy4[DC__NUM_DPP__MAX];
- int dummy5[DC__NUM_DPP__MAX];
- int dummy6[DC__NUM_DPP__MAX];
+ unsigned int dummy5[DC__NUM_DPP__MAX];
+ unsigned int dummy6[DC__NUM_DPP__MAX];
bool dummy7[DC__NUM_DPP__MAX];
bool dummysinglestring;
@@ -3429,7 +3429,7 @@ static void CalculateVupdateAndDynamicMe
double *Tdmbf,
double *Tdmec,
double *Tdmsks,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
@@ -3783,7 +3783,7 @@ static noinline void CalculatePrefetchSc
&v->VReadyOffsetPix[k]);
}
-static void PatchDETBufferSizeInKByte(unsigned int NumberOfActivePlanes, int NoOfDPPThisState[], unsigned int config_return_buffer_size_in_kbytes, unsigned int DETBufferSizeInKByte[])
+static void PatchDETBufferSizeInKByte(unsigned int NumberOfActivePlanes, unsigned int NoOfDPPThisState[], unsigned int config_return_buffer_size_in_kbytes, unsigned int DETBufferSizeInKByte[])
{
int total_pipes = 0;
unsigned int i;
@@ -3804,7 +3804,7 @@ void dml31_ModeSupportAndSystemConfigura
int idx;
unsigned int i, j, k, m;
int ReorderingBytes;
- int MinPrefetchMode = 0, MaxPrefetchMode = 2;
+ unsigned int MinPrefetchMode = 0, MaxPrefetchMode = 2;
bool NoChroma = true;
bool EnoughWritebackUnits = true;
bool P2IWith420 = false;
@@ -5119,7 +5119,7 @@ void dml31_ModeSupportAndSystemConfigura
double HostVMInefficiencyFactor = 1;
int NextPrefetchModeState = MinPrefetchMode;
bool UnboundedRequestEnabledThisState = false;
- int CompressedBufferSizeInkByteThisState = 0;
+ unsigned int CompressedBufferSizeInkByteThisState = 0;
double dummy;
v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j];
@@ -5774,8 +5774,8 @@ static void CalculateWatermarksAndDRAMSp
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -5926,7 +5926,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
@@ -6050,35 +6050,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -6223,18 +6223,18 @@ static void CalculateVMGroupAndRequestTi
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -6342,29 +6342,29 @@ static void CalculateStutterEfficiency(
bool ProgressiveToInterlaceUnitInOPP,
bool Interlace[],
double MinTTUVBlank[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double NetDCCRateLuma[],
double NetDCCRateChroma[],
double DCCFractionOfZeroSizeRequestsLuma[],
double DCCFractionOfZeroSizeRequestsChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -6649,42 +6649,42 @@ static void CalculateSwathAndDETConfigur
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
bool *ViewportSizeSupport)
{
(void)HRatioChroma;
- int MaximumSwathHeightY[DC__NUM_DPP__MAX];
- int MaximumSwathHeightC[DC__NUM_DPP__MAX];
- int MinimumSwathHeightY;
- int MinimumSwathHeightC;
+ unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX];
+ unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX];
+ unsigned int MinimumSwathHeightY;
+ unsigned int MinimumSwathHeightC;
unsigned int RoundedUpMaxSwathSizeBytesY;
unsigned int RoundedUpMaxSwathSizeBytesC;
unsigned int RoundedUpMinSwathSizeBytesY;
@@ -6829,31 +6829,31 @@ static void CalculateSwathWidth(
int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
- int HActive[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[])
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[])
{
(void)BytePerPixY;
enum odm_combine_mode MainPlaneODMCombine;
@@ -6960,8 +6960,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels)
@@ -7006,8 +7006,8 @@ static double CalculateExtraLatencyBytes
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels)
@@ -7061,7 +7061,7 @@ static noinline_for_stack void UseMinimu
int ReorderingBytes)
{
struct vba_vars_st *v = &mode_lib->vba;
- int dummy1;
+ unsigned int dummy1;
unsigned int j, k;
unsigned int i;
double NormalEfficiency, dummy2, dummy3;
@@ -7081,7 +7081,7 @@ static noinline_for_stack void UseMinimu
double ExtraLatencyBytes;
double ExtraLatencyCycles;
double DCFCLKRequiredForPeakBandwidth;
- int NoOfDPPState[DC__NUM_DPP__MAX];
+ unsigned int NoOfDPPState[DC__NUM_DPP__MAX];
double MinimumTvmPlus2Tr0;
TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
@@ -7226,7 +7226,7 @@ static void CalculateUnboundedRequestAnd
int CompressedBufferSegmentSizeInkByteFinal,
enum output_encoder_class *Output,
bool *UnboundedRequestEnabled,
- int *CompressedBufferSizeInkByte)
+ unsigned int *CompressedBufferSizeInkByte)
{
double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64);
@@ -7244,7 +7244,7 @@ static void CalculateUnboundedRequestAnd
dml_print("DML::%s: UseUnboundedRequestingFinal = %d\n", __func__, UseUnboundedRequestingFinal);
dml_print("DML::%s: actDETBufferSizeInKByte = %f\n", __func__, actDETBufferSizeInKByte);
dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, *UnboundedRequestEnabled);
- dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte);
+ dml_print("DML::%s: CompressedBufferSizeInkByte = %u\n", __func__, *CompressedBufferSizeInkByte);
#endif
}
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -166,7 +166,7 @@ static bool CalculatePrefetchSchedule(
double *Tdmdl_vm,
double *Tdmdl,
double *TSetup,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix);
static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
@@ -227,19 +227,19 @@ static unsigned int CalculateVMAndRowByt
unsigned int *MetaRowByte,
unsigned int *PixelPTEBytesPerRow,
bool *PTEBufferSizeNotExceeded,
- int *dpte_row_width_ub,
+ unsigned int *dpte_row_width_ub,
unsigned int *dpte_row_height,
unsigned int *MetaRequestWidth,
unsigned int *MetaRequestHeight,
unsigned int *meta_row_width,
unsigned int *meta_row_height,
- int *vm_group_bytes,
+ unsigned int *vm_group_bytes,
unsigned int *dpte_group_bytes,
unsigned int *PixelPTEReqWidth,
unsigned int *PixelPTEReqHeight,
unsigned int *PTERequestSize,
- int *DPDE0BytesFrame,
- int *MetaPTEBytesFrame);
+ unsigned int *DPDE0BytesFrame,
+ unsigned int *MetaPTEBytesFrame);
static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime);
static void CalculateRowBandwidth(
bool GPUVMEnable,
@@ -294,7 +294,7 @@ static void CalculateVupdateAndDynamicMe
double *Tdmbf,
double *Tdmec,
double *Tdmsks,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix);
@@ -327,8 +327,8 @@ static void CalculateWatermarksAndDRAMSp
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -386,7 +386,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
@@ -411,35 +411,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -462,18 +462,18 @@ static void CalculateVMGroupAndRequestTi
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -501,29 +501,29 @@ static void CalculateStutterEfficiency(
bool ProgressiveToInterlaceUnitInOPP,
bool Interlace[],
double MinTTUVBlank[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double NetDCCRateLuma[],
double NetDCCRateChroma[],
double DCCFractionOfZeroSizeRequestsLuma[],
double DCCFractionOfZeroSizeRequestsChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -547,32 +547,32 @@ static void CalculateSwathAndDETConfigur
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
@@ -582,31 +582,31 @@ static void CalculateSwathWidth(
int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
- int HActive[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[]);
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[]);
static double CalculateExtraLatency(
int RoundTripPingLatencyCycles,
@@ -620,8 +620,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels);
@@ -635,8 +635,8 @@ static double CalculateExtraLatencyBytes
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels);
@@ -660,7 +660,7 @@ static void CalculateUnboundedRequestAnd
int CompressedBufferSegmentSizeInkByteFinal,
enum output_encoder_class *Output,
bool *UnboundedRequestEnabled,
- int *CompressedBufferSizeInkByte);
+ unsigned int *CompressedBufferSizeInkByte);
static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output);
static unsigned int CalculateMaxVStartup(
@@ -887,7 +887,7 @@ static bool CalculatePrefetchSchedule(
double *Tdmdl_vm,
double *Tdmdl,
double *TSetup,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
@@ -1835,19 +1835,19 @@ static unsigned int CalculateVMAndRowByt
unsigned int *MetaRowByte,
unsigned int *PixelPTEBytesPerRow,
bool *PTEBufferSizeNotExceeded,
- int *dpte_row_width_ub,
+ unsigned int *dpte_row_width_ub,
unsigned int *dpte_row_height,
unsigned int *MetaRequestWidth,
unsigned int *MetaRequestHeight,
unsigned int *meta_row_width,
unsigned int *meta_row_height,
- int *vm_group_bytes,
+ unsigned int *vm_group_bytes,
unsigned int *dpte_group_bytes,
unsigned int *PixelPTEReqWidth,
unsigned int *PixelPTEReqHeight,
unsigned int *PTERequestSize,
- int *DPDE0BytesFrame,
- int *MetaPTEBytesFrame)
+ unsigned int *DPDE0BytesFrame,
+ unsigned int *MetaPTEBytesFrame)
{
(void)SourcePixelFormat;
struct vba_vars_st *v = &mode_lib->vba;
@@ -3297,18 +3297,18 @@ static void DisplayPipeConfiguration(str
// Display Pipe Configuration
double BytePerPixDETY[DC__NUM_DPP__MAX];
double BytePerPixDETC[DC__NUM_DPP__MAX];
- int BytePerPixY[DC__NUM_DPP__MAX];
- int BytePerPixC[DC__NUM_DPP__MAX];
- int Read256BytesBlockHeightY[DC__NUM_DPP__MAX];
- int Read256BytesBlockHeightC[DC__NUM_DPP__MAX];
- int Read256BytesBlockWidthY[DC__NUM_DPP__MAX];
- int Read256BytesBlockWidthC[DC__NUM_DPP__MAX];
+ unsigned int BytePerPixY[DC__NUM_DPP__MAX];
+ unsigned int BytePerPixC[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX];
double dummy1[DC__NUM_DPP__MAX];
double dummy2[DC__NUM_DPP__MAX];
double dummy3[DC__NUM_DPP__MAX];
double dummy4[DC__NUM_DPP__MAX];
- int dummy5[DC__NUM_DPP__MAX];
- int dummy6[DC__NUM_DPP__MAX];
+ unsigned int dummy5[DC__NUM_DPP__MAX];
+ unsigned int dummy6[DC__NUM_DPP__MAX];
bool dummy7[DC__NUM_DPP__MAX];
bool dummysinglestring;
@@ -3535,7 +3535,7 @@ static void CalculateVupdateAndDynamicMe
double *Tdmbf,
double *Tdmec,
double *Tdmsks,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
@@ -3897,7 +3897,7 @@ void dml314_ModeSupportAndSystemConfigur
unsigned int i;
unsigned int k, m;
int ReorderingBytes;
- int MinPrefetchMode = 0, MaxPrefetchMode = 2;
+ unsigned int MinPrefetchMode = 0, MaxPrefetchMode = 2;
bool NoChroma = true;
bool EnoughWritebackUnits = true;
bool P2IWith420 = false;
@@ -5205,7 +5205,7 @@ void dml314_ModeSupportAndSystemConfigur
double HostVMInefficiencyFactor = 1;
int NextPrefetchModeState = MinPrefetchMode;
bool UnboundedRequestEnabledThisState = false;
- int CompressedBufferSizeInkByteThisState = 0;
+ unsigned int CompressedBufferSizeInkByteThisState = 0;
double dummy;
v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j];
@@ -5867,8 +5867,8 @@ static void CalculateWatermarksAndDRAMSp
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -6019,7 +6019,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
@@ -6144,35 +6144,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -6317,18 +6317,18 @@ static void CalculateVMGroupAndRequestTi
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -6436,29 +6436,29 @@ static void CalculateStutterEfficiency(
bool ProgressiveToInterlaceUnitInOPP,
bool Interlace[],
double MinTTUVBlank[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double NetDCCRateLuma[],
double NetDCCRateChroma[],
double DCCFractionOfZeroSizeRequestsLuma[],
double DCCFractionOfZeroSizeRequestsChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -6742,40 +6742,40 @@ static void CalculateSwathAndDETConfigur
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
bool *ViewportSizeSupport)
{
(void)HRatioChroma;
- int MaximumSwathHeightY[DC__NUM_DPP__MAX];
- int MaximumSwathHeightC[DC__NUM_DPP__MAX];
+ unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX];
+ unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX];
int MinimumSwathHeightY;
int MinimumSwathHeightC;
unsigned int RoundedUpMaxSwathSizeBytesY;
@@ -6919,31 +6919,31 @@ static void CalculateSwathWidth(
int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
- int HActive[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[])
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[])
{
(void)BytePerPixY;
enum odm_combine_mode MainPlaneODMCombine;
@@ -7049,8 +7049,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels)
@@ -7095,8 +7095,8 @@ static double CalculateExtraLatencyBytes
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels)
@@ -7147,7 +7147,7 @@ static noinline_for_stack void UseMinimu
int ReorderingBytes)
{
struct vba_vars_st *v = &mode_lib->vba;
- int dummy1, j;
+ unsigned int dummy1, j;
unsigned int i, k;
double NormalEfficiency, dummy2, dummy3;
double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
@@ -7166,7 +7166,7 @@ static noinline_for_stack void UseMinimu
double ExtraLatencyBytes;
double ExtraLatencyCycles;
double DCFCLKRequiredForPeakBandwidth;
- int NoOfDPPState[DC__NUM_DPP__MAX];
+ unsigned int NoOfDPPState[DC__NUM_DPP__MAX];
double MinimumTvmPlus2Tr0;
TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
@@ -7314,7 +7314,7 @@ static void CalculateUnboundedRequestAnd
int CompressedBufferSegmentSizeInkByteFinal,
enum output_encoder_class *Output,
bool *UnboundedRequestEnabled,
- int *CompressedBufferSizeInkByte)
+ unsigned int *CompressedBufferSizeInkByte)
{
double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64);
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1397,7 +1397,7 @@ static void try_odm_power_optimization_a
display_e2e_pipe_params_st *pipes,
int *split,
bool *merge,
- unsigned int *vlevel,
+ int *vlevel,
int pipe_cnt)
{
int i;
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -2954,7 +2954,7 @@ void dml32_UseMinimumDCFCLK(
unsigned int VTotal[],
unsigned int VActive[],
unsigned int DynamicMetadataTransmittedBytes[],
- unsigned int DynamicMetadataLinesBeforeActiveRequired[],
+ int DynamicMetadataLinesBeforeActiveRequired[],
bool Interlace[],
double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX],
double RequiredDISPCLK[][2],
@@ -5631,7 +5631,7 @@ void dml32_CalculateStutterEfficiency(
bool Interlace[],
double MinTTUVBlank[],
unsigned int DPPPerSurface[],
- unsigned int DETBufferSizeY[],
+ unsigned int DETBufferSizeY[],
unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
@@ -5663,10 +5663,10 @@ void dml32_CalculateStutterEfficiency(
/* Output */
double *StutterEfficiencyNotIncludingVBlank,
double *StutterEfficiency,
- unsigned int *NumberOfStutterBurstsPerFrame,
+ int *NumberOfStutterBurstsPerFrame,
double *Z8StutterEfficiencyNotIncludingVBlank,
double *Z8StutterEfficiency,
- unsigned int *Z8NumberOfStutterBurstsPerFrame,
+ int *Z8NumberOfStutterBurstsPerFrame,
double *StutterPeriod,
bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE)
{
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -614,7 +614,7 @@ void dml32_UseMinimumDCFCLK(
unsigned int VTotal[],
unsigned int VActive[],
unsigned int DynamicMetadataTransmittedBytes[],
- unsigned int DynamicMetadataLinesBeforeActiveRequired[],
+ int DynamicMetadataLinesBeforeActiveRequired[],
bool Interlace[],
double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX],
double RequiredDISPCLK[][2],
@@ -1013,7 +1013,7 @@ void dml32_CalculateStutterEfficiency(
bool ProgressiveToInterlaceUnitInOPP,
bool Interlace[],
double MinTTUVBlank[],
- unsigned int DPPPerSurface[],
+ unsigned int DPPPerSurface[],
unsigned int DETBufferSizeY[],
unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
@@ -1046,10 +1046,10 @@ void dml32_CalculateStutterEfficiency(
/* Output */
double *StutterEfficiencyNotIncludingVBlank,
double *StutterEfficiency,
- unsigned int *NumberOfStutterBurstsPerFrame,
+ int *NumberOfStutterBurstsPerFrame,
double *Z8StutterEfficiencyNotIncludingVBlank,
double *Z8StutterEfficiency,
- unsigned int *Z8NumberOfStutterBurstsPerFrame,
+ int *Z8NumberOfStutterBurstsPerFrame,
double *StutterPeriod,
bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -472,7 +472,7 @@ struct vba_vars_st {
unsigned int VTotal[DC__NUM_DPP__MAX];
unsigned int VTotal_Max[DC__NUM_DPP__MAX];
unsigned int VTotal_Min[DC__NUM_DPP__MAX];
- int DPPPerPlane[DC__NUM_DPP__MAX];
+ unsigned int DPPPerPlane[DC__NUM_DPP__MAX];
double PixelClock[DC__NUM_DPP__MAX];
double PixelClockBackEnd[DC__NUM_DPP__MAX];
bool DCCEnable[DC__NUM_DPP__MAX];
@@ -739,7 +739,7 @@ struct vba_vars_st {
/* ms locals */
double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2];
unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
- int NoOfDPPThisState[DC__NUM_DPP__MAX];
+ unsigned int NoOfDPPThisState[DC__NUM_DPP__MAX];
enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
double SwathWidthYThisState[DC__NUM_DPP__MAX];
unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
@@ -900,7 +900,7 @@ struct vba_vars_st {
int PTEBufferSizeInRequestsForChroma;
// Missing from VBA
- int dpte_group_bytes_chroma;
+ unsigned int dpte_group_bytes_chroma;
unsigned int vm_group_bytes_chroma;
double dst_x_after_scaler;
double dst_y_after_scaler;
@@ -1100,8 +1100,8 @@ struct vba_vars_st {
unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX];
bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
- int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
- int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
+ unsigned int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
+ unsigned int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
double UrgLatency[DC__VOLTAGE_STATES];
double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
@@ -1172,7 +1172,7 @@ struct vba_vars_st {
int ConfigReturnBufferSizeInKByte;
enum unbounded_requesting_policy UseUnboundedRequesting;
int CompressedBufferSegmentSizeInkByte;
- int CompressedBufferSizeInkByte;
+ unsigned int CompressedBufferSizeInkByte;
int MetaFIFOSizeInKEntries;
int ZeroSizeBufferEntries;
int COMPBUF_RESERVED_SPACE_64B;
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
@@ -307,7 +307,7 @@ void dpp1_cm_set_output_csc_default(
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
const uint16_t *regval = NULL;
- int arr_size;
+ uint32_t arr_size;
regval = find_color_matrix(colorspace, &arr_size);
if (regval == NULL) {
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
@@ -543,7 +543,7 @@ bool dpp3_get_optimal_number_of_taps(
static void dpp3_deferred_update(struct dpp *dpp_base)
{
- int bypass_state;
+ uint32_t bypass_state;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
if (dpp_base->deferred_reg_writes.bits.disable_dscl) {
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
@@ -317,7 +317,7 @@ void dpp3_set_hdr_multiplier(
static void program_gamut_remap(
struct dcn3_dpp *dpp,
const uint16_t *regval,
- int select)
+ unsigned int select)
{
uint16_t selection = 0;
struct color_matrices_reg gam_regs;
@@ -379,7 +379,7 @@ void dpp3_cm_set_gamut_remap(
{
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
int i = 0;
- int gamut_mode;
+ uint32_t gamut_mode;
if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
/* Bypass if type is bypass or hw */
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -1333,7 +1333,7 @@ uint32_t dc_dsc_stream_bandwidth_in_kbps
uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(
const struct dc_crtc_timing *timing,
- const int num_slices_h,
+ const uint32_t num_slices_h,
const bool is_dp)
{
struct fixed31_32 max_dsc_overhead;
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
@@ -227,9 +227,9 @@ bool dsc2_get_packed_pps(struct display_
void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
{
struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
- int dsc_clock_en;
- int dsc_fw_config;
- int enabled_opp_pipe;
+ uint32_t dsc_clock_en;
+ uint32_t dsc_fw_config;
+ uint32_t enabled_opp_pipe;
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
@@ -252,7 +252,7 @@ void dsc2_enable(struct display_stream_c
void dsc2_disable(struct display_stream_compressor *dsc)
{
struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
- int dsc_clock_en;
+ uint32_t dsc_clock_en;
DC_LOG_DSC("disable DSC %d", dsc->inst);
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
@@ -79,9 +79,9 @@ void dsc35_construct(struct dcn20_dsc *d
static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe)
{
struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
- int dsc_clock_en;
- int dsc_fw_config;
- int enabled_opp_pipe;
+ uint32_t dsc_clock_en;
+ uint32_t dsc_fw_config;
+ uint32_t enabled_opp_pipe;
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
@@ -96,7 +96,7 @@ static void dsc35_enable(struct display_
REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
- DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
+ DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe);
ASSERT(0);
}
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
@@ -144,16 +144,16 @@ void dsc401_set_config(struct display_st
void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe)
{
struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
- int dsc_clock_en;
- int dsc_fw_config;
- int enabled_opp_pipe;
+ uint32_t dsc_clock_en;
+ uint32_t dsc_fw_config;
+ uint32_t enabled_opp_pipe;
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
- DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
+ DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe);
ASSERT(0);
}
@@ -169,7 +169,7 @@ void dsc401_enable(struct display_stream
void dsc401_disable(struct display_stream_compressor *dsc)
{
struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
- int dsc_clock_en;
+ uint32_t dsc_clock_en;
DC_LOG_DSC("disable DSC %d", dsc->inst);
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
@@ -63,10 +63,10 @@ void hubp401_enable_3dlut_fl(struct hubp
REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, enable ? 1 : 0);
}
-int hubp401_get_3dlut_fl_done(struct hubp *hubp)
+uint32_t hubp401_get_3dlut_fl_done(struct hubp *hubp)
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
- int ret;
+ uint32_t ret;
REG_GET(HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, &ret);
return ret;
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
@@ -324,7 +324,7 @@ bool hubp401_construct(
void hubp401_init(struct hubp *hubp);
-int hubp401_get_3dlut_fl_done(struct hubp *hubp);
+uint32_t hubp401_get_3dlut_fl_done(struct hubp *hubp);
void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable);
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -2484,7 +2484,8 @@ void dcn10_enable_vblanks_synchronizatio
(void)group_index;
struct output_pixel_processor *opp;
struct timing_generator *tg;
- int i, width = 0, height = 0, master;
+ int i, master;
+ uint32_t width = 0, height = 0;
DC_LOGGER_INIT(dc->ctx);
@@ -2550,7 +2551,8 @@ void dcn10_enable_timing_synchronization
(void)group_index;
struct output_pixel_processor *opp;
struct timing_generator *tg;
- int i, width = 0, height = 0;
+ int i;
+ uint32_t width = 0, height = 0;
DC_LOGGER_INIT(dc->ctx);
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -147,7 +147,7 @@ static void update_dsc_on_stream(struct
// Given any pipe_ctx, return the total ODM combine factor, and optionally return
// the OPPids which are used
-static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
+static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances)
{
unsigned int opp_count = 1;
struct pipe_ctx *odm_pipe;
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1119,7 +1119,7 @@ void dcn32_update_dsc_on_stream(struct p
* Given any pipe_ctx, return the total ODM combine factor, and optionally return
* the OPPids which are used
* */
-static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
+static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances)
{
unsigned int opp_count = 1;
struct pipe_ctx *odm_pipe;
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -403,7 +403,7 @@ static void update_dsc_on_stream(struct
// Given any pipe_ctx, return the total ODM combine factor, and optionally return
// the OPPids which are used
-static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
+static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances)
{
unsigned int opp_count = 1;
struct pipe_ctx *odm_pipe;
--- a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
@@ -126,7 +126,7 @@ static inline struct bw_fixed bw_div(con
static inline struct bw_fixed bw_mod(const struct bw_fixed arg1, const struct bw_fixed arg2)
{
struct bw_fixed res;
- div64_u64_rem(arg1.value, arg2.value, (uint64_t *)&res.value);
+ div64_u64_rem((uint64_t)arg1.value, (uint64_t)arg2.value, (uint64_t *)&res.value);
return res;
}
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -305,7 +305,7 @@ struct hubp_funcs {
enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g,
enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b,
enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r);
- int (*hubp_get_3dlut_fl_done)(struct hubp *hubp);
+ uint32_t (*hubp_get_3dlut_fl_done)(struct hubp *hubp);
void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg);
void (*hubp_clear_tiling)(struct hubp *hubp);
uint32_t (*hubp_get_current_read_line)(struct hubp *hubp);
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -356,8 +356,8 @@ struct opp_funcs {
void (*opp_program_dpg_dimensions)(
struct output_pixel_processor *opp,
- int width,
- int height);
+ uint32_t width,
+ uint32_t height);
bool (*dpg_is_blanked)(
struct output_pixel_processor *opp);
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -32,9 +32,9 @@ struct dc_bios;
/* Contains CRTC vertical/horizontal pixel counters */
struct crtc_position {
- int32_t vertical_count;
- int32_t horizontal_count;
- int32_t nominal_vcount;
+ uint32_t vertical_count;
+ uint32_t horizontal_count;
+ uint32_t nominal_vcount;
};
struct dcp_gsl_params {
@@ -321,7 +321,7 @@ struct timing_generator {
const struct timing_generator_funcs *funcs;
struct dc_bios *bp;
struct dc_context *ctx;
- int inst;
+ uint32_t inst;
};
struct dc_crtc_timing;
--- a/drivers/gpu/drm/amd/display/dc/inc/link_service.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_service.h
@@ -110,7 +110,7 @@ struct link_service {
struct dc_sink *(*add_remote_sink)(
struct dc_link *link,
const uint8_t *edid,
- int len,
+ unsigned int len,
struct dc_sink_init_data *init_data);
void (*remove_remote_sink)(struct dc_link *link, struct dc_sink *sink);
bool (*get_hpd_state)(struct dc_link *link);
--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
@@ -155,63 +155,63 @@
* read given register and fill in field value in output parameter */
#define REG_GET(reg_name, field, val) \
generic_reg_get(CTX, REG(reg_name), \
- FN(reg_name, field), val)
+ FN(reg_name, field), (uint32_t *)val)
#define REG_GET_2(reg_name, f1, v1, f2, v2) \
generic_reg_get2(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2)
#define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \
generic_reg_get3(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3)
#define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \
generic_reg_get4(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3, \
- FN(reg_name, f4), v4)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3, \
+ FN(reg_name, f4), (uint32_t *)v4)
#define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
generic_reg_get5(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3, \
- FN(reg_name, f4), v4, \
- FN(reg_name, f5), v5)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3, \
+ FN(reg_name, f4), (uint32_t *)v4, \
+ FN(reg_name, f5), (uint32_t *)v5)
#define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
generic_reg_get6(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3, \
- FN(reg_name, f4), v4, \
- FN(reg_name, f5), v5, \
- FN(reg_name, f6), v6)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3, \
+ FN(reg_name, f4), (uint32_t *)v4, \
+ FN(reg_name, f5), (uint32_t *)v5, \
+ FN(reg_name, f6), (uint32_t *)v6)
#define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
generic_reg_get7(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3, \
- FN(reg_name, f4), v4, \
- FN(reg_name, f5), v5, \
- FN(reg_name, f6), v6, \
- FN(reg_name, f7), v7)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3, \
+ FN(reg_name, f4), (uint32_t *)v4, \
+ FN(reg_name, f5), (uint32_t *)v5, \
+ FN(reg_name, f6), (uint32_t *)v6, \
+ FN(reg_name, f7), (uint32_t *)v7)
#define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
generic_reg_get8(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3, \
- FN(reg_name, f4), v4, \
- FN(reg_name, f5), v5, \
- FN(reg_name, f6), v6, \
- FN(reg_name, f7), v7, \
- FN(reg_name, f8), v8)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3, \
+ FN(reg_name, f4), (uint32_t *)v4, \
+ FN(reg_name, f5), (uint32_t *)v5, \
+ FN(reg_name, f6), (uint32_t *)v6, \
+ FN(reg_name, f7), (uint32_t *)v7, \
+ FN(reg_name, f8), (uint32_t *)v8)
/* macro to poll and wait for a register field to read back given value */
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -1565,7 +1565,7 @@ static bool link_add_remote_sink_helper(
struct dc_sink *link_add_remote_sink(
struct dc_link *link,
const uint8_t *edid,
- int len,
+ unsigned int len,
struct dc_sink_init_data *init_data)
{
struct dc_sink *dc_sink;
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.h
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.h
@@ -32,7 +32,7 @@ bool link_detect_connection_type(struct
struct dc_sink *link_add_remote_sink(
struct dc_link *link,
const uint8_t *edid,
- int len,
+ unsigned int len,
struct dc_sink_init_data *init_data);
void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink);
bool link_reset_cur_dp_mst_topology(struct dc_link *link);
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -47,9 +47,9 @@
#define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B
/* Travis */
-static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
+static const char DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
/* Nutmeg */
-static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
+static const char DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
{
@@ -1211,9 +1211,9 @@ int edp_get_backlight_level(const struct
fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
- return panel_cntl->funcs->get_current_backlight(panel_cntl);
+ return (int)panel_cntl->funcs->get_current_backlight(panel_cntl);
else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
- return (int) abm->funcs->get_current_backlight(abm);
+ return (int)abm->funcs->get_current_backlight(abm);
else
return DC_ERROR_UNEXPECTED;
}
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
@@ -375,7 +375,7 @@ void mpc1_mpc_init(struct mpc *mpc)
void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)
{
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
- int opp_id;
+ uint32_t opp_id;
REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
@@ -1067,7 +1067,7 @@ static void program_gamut_remap(
struct dcn30_mpc *mpc30,
int mpcc_id,
const uint16_t *regval,
- int select)
+ uint32_t select)
{
uint16_t selection = 0;
struct color_matrices_reg gam_regs;
@@ -1129,7 +1129,7 @@ void mpc3_set_gamut_remap(
{
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
int i = 0;
- int gamut_mode;
+ uint32_t gamut_mode;
if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
program_gamut_remap(mpc30, mpcc_id, NULL, GAMUT_REMAP_BYPASS);
@@ -1201,7 +1201,7 @@ void mpc3_get_gamut_remap(struct mpc *mp
{
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
uint16_t arr_reg_val[12] = {0};
- int select;
+ uint32_t select;
read_gamut_remap(mpc30, mpcc_id, arr_reg_val, &select);
--- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
@@ -293,7 +293,7 @@ void opp2_set_disp_pattern_generator(
void opp2_program_dpg_dimensions(
struct output_pixel_processor *opp,
- int width, int height)
+ uint32_t width, uint32_t height)
{
struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
--- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h
@@ -156,7 +156,7 @@ void opp2_set_disp_pattern_generator(
void opp2_program_dpg_dimensions(
struct output_pixel_processor *opp,
- int width, int height);
+ uint32_t width, uint32_t height);
bool opp2_dpg_is_blanked(struct output_pixel_processor *opp);
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
@@ -101,7 +101,7 @@ static void optc32_set_odm_combine(struc
void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments)
{
struct optc *optc1 = DCN10TG_FROM_TG(tg);
- int segments;
+ uint32_t segments;
REG_GET(OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, &segments);
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -445,7 +445,7 @@ static inline struct fixed31_32 dc_fixpt
*/
static inline int dc_fixpt_floor(struct fixed31_32 arg)
{
- unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value;
+ unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value);
if (arg.value >= 0)
return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
@@ -459,7 +459,7 @@ static inline int dc_fixpt_floor(struct
*/
static inline int dc_fixpt_round(struct fixed31_32 arg)
{
- unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value;
+ unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value);
const long long summand = dc_fixpt_half.value;
@@ -479,7 +479,7 @@ static inline int dc_fixpt_round(struct
*/
static inline int dc_fixpt_ceil(struct fixed31_32 arg)
{
- unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value;
+ unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value);
const long long summand = dc_fixpt_one.value -
dc_fixpt_epsilon.value;
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
@@ -44,7 +44,7 @@ void mod_hdcp_dump_binary_message(uint8_
for (i = 0; i < msg_size; i++) {
if (i % bytes_per_line == 0)
buf[buf_pos++] = '\n';
- sprintf(&buf[buf_pos], "%02X ", msg[i]);
+ sprintf((char *)&buf[buf_pos], "%02X ", msg[i]);
buf_pos += byte_size;
}
buf[buf_pos++] = '\0';
next prev parent reply other threads:[~2026-08-20 15:07 UTC|newest]
Thread overview: 233+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-20 14:52 [PATCH 7.1 000/228] 7.1.10-rc1 review Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 001/228] block: stop the timeout timer when releasing a never added disk Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 002/228] selinux: require every boolean value to be defined Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 003/228] selinux: reject a class permission count below its inherited common Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 004/228] selinux: do not cancel a policy conversion that never started Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 005/228] selinux: reject an unclaimed class value in security_get_classes() Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 006/228] selinux: reject a permission value exceeding the class permission count Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 007/228] mptcp: reclaim forward-allocated memory on RX path errors Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 008/228] selftests: mptcp: join: mark tests with data corruption as failed Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 009/228] mptcp: avoid combining some incoming suboptions Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 010/228] mptcp: options: reset DSS fields in case of unexpected size Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 011/228] mptcp: pm: fix data race in add_addr timer callback Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 012/228] mptcp: fastopen: only mark MPTFO subflows with SYN data Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 013/228] s390/qeth: validate user buffer length in SNMP and ARP query ioctls Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 014/228] microblaze: restore the page alignment of swapper_pg_dir Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 015/228] ASoC: codecs: lpass-tx-macro: Fix enum kcontrol accesses Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 016/228] drm/shmem_helper: Check VMA boundaries for PMD mappings Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 017/228] ASoC: SOF: sof-audio: Fix error path in sof_widget_setup_unlocked() Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 018/228] ASoC: SOF: ipc4-pcm: Continue the pipeline trigger in case of IPC timeout Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 019/228] ASoC: cs4265: sort the register default table Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 020/228] ASoC: cs35l45: " Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 021/228] ASoC: cs35l41: " Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 022/228] ASoC: codecs: lpass-wsa-macro: Fix enum kcontrol accesses Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 023/228] fbdev: bound mode sysfs output to the sysfs buffer Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 024/228] fbdev: clear fb_info->mode before deleting a videomode Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 025/228] fbdev: core: Fix pointer desynchronization in fb_io_read() Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 026/228] drm/panthor: skip zero-sized firmware sections Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 027/228] drm/amdgpu: reject oversized IBs with per-ring packet limits Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 028/228] drm/amdgpu: read TRUNCATE_COORD_MODE on gfx12 Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 029/228] drm/amdgpu/userq: serialize queue map against GPU reset Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 030/228] drm/amd: Disable DP audio spread spectrum for Cyan Skillfish Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 031/228] drm/radeon: restore hardware polling in fence_is_signaled to fix performance regression Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 032/228] drm/amdgpu: Use virtual alloc during coredump Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 033/228] drm/amdgpu: fix JPEG v5.3.0 queue reset failure in DPG mode Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 034/228] drm/amdgpu: fix JPEG v5.0.0 " Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 035/228] drm/amdgpu: fix JPEG v4.0.5 " Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 036/228] drm/amdgpu: fix aperture iounmap skipped on device removal Greg Kroah-Hartman
2026-08-20 14:52 ` [PATCH 7.1 037/228] drm/amdgpu/gmc12.1: implement tlb inv semaphore Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 038/228] drm/amdgpu/gmc12.1: fix MMHUB0 check in pasid tlb flush Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 039/228] ASoC: SOF: topology: Use acpi mach from the machine driver Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 040/228] Input: xpad - add support for ZENAIM LEVERLESS Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 041/228] Input: cs40l50-vibra - validate custom data from user space Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 042/228] powerpc/pseries: pci - logic bug Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 043/228] Input: synaptics-rmi4 - fix F55 transmitter electrode count typo Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 044/228] Input: focaltech - fix array out-of-bounds in focaltech_process_rel_packet Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 045/228] Input: psxpad-spi - set driver data before use Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 046/228] Input: atkbd - skip deactivate for Xiaomi Book Pro 14s internal keyboard Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 047/228] Input: atkbd - skip deactivate for HONOR ZQC-P Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 048/228] Input: iforce - validate input packet lengths Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 049/228] Input: byd - synchronize timer deletion before freeing private data Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 050/228] powerpc/pseries: lparcfg - fix kbuf[] underflow Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 051/228] powerpc/pseries: papr-phy-attest - validate cmd.length, plug mem leak Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 052/228] Input: synaptics-rmi4 - zero report size on F54 work error Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 053/228] Input: synaptics-rmi4 - bound the F54 report size to the allocated buffer Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 054/228] Input: synaptics-rmi4 - block s_input when F54 queue is busy Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 055/228] Input: synaptics-rmi4 - propagate F54 worker errors to V4L2 queue Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 056/228] Input: hynitron_cstxxx - validate touch count and finger IDs Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 057/228] crypto: starfive - use scatterlist length before DMA mapping Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 058/228] crypto: qce - fix error path in devm_qce_register_algs Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 059/228] gve: fix NULL dereference due to missing ptp adjfine Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 060/228] gpio: sloppy-logic-analyzer: fix use-after-free via debugfs trigger on unbind Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 061/228] selftests/ftrace: Convert ELF entry point to file offset in uprobe test Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 062/228] gve: fix zero-length skb frag with header-split Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 063/228] gpio: ml-ioh: use raw_spinlock_t for the register lock Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 064/228] pmdomain: qcom: rpmhpd: Add missing MXC and MMCX power domains for Eliza Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 065/228] pmdomain: arm: Fix -EINVAL from scmi_pd_set_perf_state() on state 0 Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 066/228] libceph: fix multiple unsafe decodes in decode_locker() Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 067/228] pmdomain: mediatek: mfg: initialize prev_o in mtk_mfg_attach_dev() Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 068/228] ftrace: Protect direct_functions in ftrace_find_rec_direct Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 069/228] ftrace: Protect direct_functions in update_ftrace_direct_del Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 070/228] ftrace: Protect direct_functions in update_ftrace_direct_mod Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 071/228] ftrace: Fix off-by-one fentry site disable in ftrace_free_mem() Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 072/228] openrisc: signal: do not restore privileged SR bits on sigreturn Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 073/228] Input: sur40 - fix input device registration ordering Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 074/228] Input: sur40 - fix V4L error path cleanup Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 075/228] libceph: Avoid using invalid osd indices from primary_temp Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 076/228] ceph: fix MDS random selection readiness predicate Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 077/228] libceph: fix OOB read in decode_watchers() via missing bounds check Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 078/228] libceph: tolerate addrvecs with multiple entries of the same type Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 079/228] mmc: omap_hsmmc: fix busy_timeout overflow in ns conversion on 32-bit Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 080/228] mmc: sdhci: unmap the bounce buffer before device release Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 081/228] pmdomain: mediatek: fix remaining %pOF after of_node_put() Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 082/228] mmc: sdhci: make tuning_err a signed int Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 083/228] pmdomains: mediatek: Avoid setting RTFFs CLK_DIS before NRESTORE Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 084/228] mmc: atmel-mci: Fix use-after-free in atmci_remove due to race condition Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 085/228] drm/connector/hdmi: Fix out of bounds memory read Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 086/228] mmc: loongson2: Fix sg iteration in data reorder functions Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 087/228] pmdomain: mediatek: Fix mt8183 hang on boot Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 088/228] riscv: hwprobe: Register unaligned probes before usermode Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 089/228] drm/xe: Order ring writes before ring tail updates Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 090/228] drm/xe: Fix xe_device_probe() failure Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 091/228] drm/xe/guc_ads: allocate UM queues in a separate BO Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 092/228] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 093/228] drm/xe/guc_ads: use uncached mapping for UM queue BO Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 094/228] drm/radeon: fix autosuspend cleanup during teardown Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 095/228] s390/vfio_ccw: Free all memory if cp_init() fails Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 096/228] s390/vfio_ccw: Limit the number of channel program segments Greg Kroah-Hartman
2026-08-20 14:53 ` [PATCH 7.1 097/228] s390/vfio_ccw: Cancel existing workqueues Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 098/228] s390/vfio_ccw: Ensure index for read/write regions are within range Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 099/228] s390/vfio_ccw: Ensure first IDAW remains constant Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 100/228] s390/vfio_ccw: Fix out of bounds check on CCW array Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 101/228] s390/vfio_ccw: Move cp cleanup out of not operational Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 102/228] s390/vfio_ccw: Selectively expand io_mutex Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 103/228] s390/vfio_ccw: Calculate idal length based on idaw type Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 104/228] s390/vfio_ccw: Implement a crw lock Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 105/228] s390/zcrypt: Fix CPRB memory allocation in zcrypt misc code Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 106/228] s390/zcrypt: Improve CCA CPRB length and overflow checks Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 107/228] s390/zcrypt: Improve EP11 " Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 108/228] s390/zcrypt: Improve EP11 CPRB domain handling with ASN.1 parsing Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 109/228] s390/zcrypt: Pad trailing CCA or EP11 message with zeros Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 110/228] drm/amd/display: Fix NULL pointer dereference in amdgpu_dm_crtc_set_vblank() Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 111/228] drm/amd/display: fix BT.2020 YCbCr limited output CSC matrix Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 112/228] drm/amd/display: fix BT.2020 YCbCr output CSC matrices for DCE Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 113/228] drm/amdgpu: Reject UVD message with invalid number of h265 refs Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 114/228] drm/amdgpu: Prefer default discovery offset Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 115/228] drm/amdgpu: fix nbif 6.3.1 l1 low power not functional Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 116/228] drm/amdgpu: fix missing check in vm_flush() Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 117/228] drm/amdgpu: check ASPM on the dGPU host link Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 118/228] drm/amdgpu: validate GEM_CREATE domain combinations Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 119/228] drm/amdgpu: Reject UVD message with dimensions above 4096 Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 120/228] drm/amdgpu: Implement insert_end for VCE 3 Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 121/228] drm/amdgpu: Fix UVD min buffer sizes Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 122/228] drm/amdgpu: Fix UVD dpb min size calculation for H264 Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 123/228] drm/amdgpu: Fix UVD decode image min size calculation Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 124/228] drm/amdgpu: disallow multiple FENCE chunks in one submit Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 125/228] xfs: propagate errors from xfs_rtginode_load Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 126/228] xfs: fix off-by-one in rtrefcount btree root level validation Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 127/228] xfs: bounds-check buffer log items dirty bitmap Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 128/228] xfs: mark nonzero sb_gquotino as corrupt on metadir filesystems Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 129/228] xfs: clear zapped attr fork state when bmap repair finds no attr fork Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 130/228] xfs: check cowextsize in xrep_inode_cowextsize Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 131/228] xfs: fix transaction block reservation in xrep_rtbitmap Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 132/228] xfs: zero i_nlink before repair puts inode on unlinked list Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 133/228] xfs: only check mergeability of bnobt records Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 134/228] xfs: dont double-lock when deleting a self-referential directory Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 135/228] xfs: set the prev pointer when reinserting an inode on the unlinked list Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 136/228] xfs: pass runtime errors from xrep_iunlink_mark_ondisk_rec up to callers Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 137/228] xfs: nlink scrub must take IOLOCK before determining ILOCK state Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 138/228] xfs: load next_agino from the correct xfarray in xrep_iunlink_relink_prev Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 139/228] xfs: fix ilock leak on error in xfs_dq_get_next_id Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 140/228] xfs: dont zap the attr fork on repair when there are queued pptr updates Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 141/228] xfs: dont walk off the end of a null sc->sa.agi_bp in AGI repair Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 142/228] xfs: fix allocated inodes that show up in the unlinked list Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 143/228] xfs: fix another iunlink infinite loop bug in online fsck Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 144/228] xfs: dont return EFSCORRUPTED when scrubbing corrupt parent pointers Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 145/228] xfs: avoid UAF on sc->tempip in xrep_tempfile_create Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 146/228] xfs: fix exchange-range reflink flag clearing issue with INO1_WRITTEN Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 147/228] xfs: dont swallow dquot recovery verification errors Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 148/228] xfs: dont ignore runtime errors in xrep_iunlink_reload_next Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 149/228] xfs: check xfarray iteration errors when committing unlinked inode lists Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 150/228] xfs: check v5 superblock features early Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 151/228] drm/amd/display: Fix type mismatches in DML and normalize loop bounds Greg Kroah-Hartman
2026-08-20 14:54 ` Greg Kroah-Hartman [this message]
2026-08-20 14:54 ` [PATCH 7.1 153/228] ceph: avoid fs reclaim while using current->journal_info Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 154/228] ceph: fix hanging __ceph_get_caps() with stale mds_wanted Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 155/228] ASoC: tas2562: Validate values for volume writes Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 156/228] drm/mediatek: Convert legacy DRM logging to drm_* helpers in mtk_dsi.c Greg Kroah-Hartman
2026-08-20 14:54 ` [PATCH 7.1 157/228] drm/mediatek: mtk_dsi: Enable HS clock only at pre-enable Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 158/228] drm/amdkfd: Add bounds check for CRAT subtype length Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 159/228] net: rename netdev_ops_assert_locked() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 160/228] net: expect instance lock in netdev_queue_get_dma_dev() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 161/228] ASoC: SOF: ipc4-topology: Refresh copier IPC payload before widget setup Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 162/228] clk: qcom: dispcc-eliza: Fix disp_cc_mdss_mdp_clk_src RCG stall on Eliza EVK Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 163/228] optee: ffa: Add NULL check in optee_ffa_lend_protmem Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 164/228] clk: spacemit: k3: fix USB2 bus clock Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 165/228] clk: spacemit: k3: set hdma clock as critical Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 166/228] arm64: tegra: Add EL2 virtual timer interrupt for Tegra194 Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 167/228] crypto: ccm - Set rfc4309 maxauthsize from child Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 168/228] crypto: tegra - fix rctx->cryptlen calculation in tegra_gcm_do_one_req() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 169/228] rhashtable: fix false-positive lockdep splat on rhltable destruction Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 170/228] gpiolib: Check gc->get_direction() before calling gpiod_get_direction() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 171/228] regulator: fp9931: Fix VPOS/VNEG voltage selector table Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 172/228] af_unix: Unlink scc_entry in unix_del_edge() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 173/228] ovpn: fix NULL dereference when killing missing key Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 174/228] ovpn: finish crypto callback cleanup before peer release Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 175/228] riscv: ftrace: Fix ftrace_modify_call failure on kprobed functions Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 176/228] scsi: core: pair EH runtime PM get and put Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 177/228] perf: Reject exited events as group leaders Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 178/228] sctp: validate cookie AUTH state before use Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 179/228] ALSA: usb-audio: Fix mixer regression on SteelSeries Arctis Nova 5 Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 180/228] riscv: lib: Fix ZBB strnlen reading past count boundary Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 181/228] ovpn: run deferred work on a module-owned workqueue Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 182/228] ovpn: defer key slot crypto freeing to workqueue Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 183/228] rseq: Prevent hard lockup on granted time slice extension Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 184/228] gpio: ml-ioh: share the register lock across channels Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 185/228] ASoC: tas2781: fix clang build error for goto bypassing cleanup variable Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 186/228] tick: Include ktime.h and jiffies.h in linux/tick.h Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 187/228] netfilter: ipset: fix refcount race between list:set GC and swap Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 188/228] ipvs: revalidate ihl to prevent out-of-bounds access Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 189/228] netfilter: nf_tables_offload: suppress WARN_ON_ONCE for ENOMEM in abort path Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 190/228] netfilter: flowtable: publish GC-visible tuple last Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 191/228] netfilter: ipset: fix list type element drift bug Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 192/228] netfilter: ipset: let destroy callbacks adjust ext mem size Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 193/228] eth: bnxt: cancel IRQ notifier before freeing affinity mask Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 194/228] eth: bnxt: keep the aRFS rmap updated when TPH is enabled Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 195/228] eth: bnxt: decrease indent in bnxt_request_irq() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 196/228] eth: bnxt: avoid deadlock when canceling IRQ affinity notifier Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 197/228] ipvlan: inherit needed_headroom and needed_tailroom from phy_dev Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 198/228] macvlan: inherit needed_headroom and needed_tailroom from lowerdev Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 199/228] veth: fix queue index used to wake the peer txq in veth_poll Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 200/228] tcp: fix icsk_ack.ato bitfield overflow Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 201/228] net: phy: realtek: fix EEE advertisement write on the internal PHY MMD path Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 202/228] net: packet: fix wrong transport_header when sending VLAN-tagged frame Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 203/228] net: tap: " Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 204/228] net: ngbe: fix NULL pointer dereference in non-MSI-X interrupt enabling Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 205/228] net/tls: Fail tls_sw_splice_read() after a failed async decrypt Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 206/228] ASoC: xilinx: formatter_pcm: pass aud_drv_data to irq handlers Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 207/228] regmap: sdw-mbq: Fix swap of timeout and retry times Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 208/228] af_packet: Dont send zero-byte data in tpacket_snd() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 209/228] net/sched: act_api: fix TOCTOU NULL deref on a->goto_chain Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 210/228] net/sched: cls_u32: skip hash tables in u32_bind_class() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 211/228] pid: reject allocations through dead ancestor pid namespaces Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 212/228] m68k: Define NR_CPUS to 1 Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 213/228] regmap: sdw-mbq: dont call an unset readable_reg callback Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 214/228] net: ethernet: ti: am65-cpsw-nuss: Fix port_id extraction from SRC TAG Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 215/228] accel/amdxdna: Skip unmapped range in aie2_populate_range() Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 216/228] net/sched: cls_bpf: reject dev-bound programs bound to a different device Greg Kroah-Hartman
2026-08-20 14:55 ` [PATCH 7.1 217/228] l2tp: fix tunnel and session refcount leak on seq_file release Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 218/228] firewire: ohci: fix NULL pointer dereference in ar_context_release Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 219/228] drm/xe/pxp: add termination on resume Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 220/228] drm/xe/oa: Fix sync entry leak on OA config emit failure Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 221/228] drm/xe/oa: Check managed mutex initialization errors Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 222/228] drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 223/228] drm/xe: Fix a bug in pc_adjust_freq_bounds() Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 224/228] drm/log: Fix division by zero when scale module parameter is 0 Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 225/228] drm/log: Fix out-of-bounds read on empty message length Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 226/228] drm/log: Fix infinite loop when scale is too large for display Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 227/228] spi: virtio: mark device ready before registering the controller Greg Kroah-Hartman
2026-08-20 14:56 ` [PATCH 7.1 228/228] erofs: fix EROFS_FS_ZIP_LZMA_DEFAULT_MAX_STREAMS on some UP platforms Greg Kroah-Hartman
2026-08-20 15:20 ` [PATCH 7.1 000/228] 7.1.10-rc1 review Brett A C Sheffield
2026-08-20 16:00 ` Ronald Warsow
2026-08-20 18:32 ` Pavel Machek
2026-08-20 21:46 ` Florian Fainelli
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