Re: [PATCH 5/6] arm64: dts: axera: add AX650 Demo initial support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Architectural incompatibility: Cortex-A55 CPUs paired with a legacy GIC-400 interrupt controller.
- [Medium] The GIC-400 node is misconfigured: incorrect CPU interface size, missing VGIC maintenance interrupt, and unit address mismatch.
- [Medium] The `cpus` node incorrectly uses `#address-cells = <1>` on an ARM64 system.
--

--- Patch [5]: [PATCH 5/6] arm64: dts: axera: add AX650 Demo initial support ---
commit 37472cfe2d70aac44a9e284715ad040433a0f768
Author: Leng Honglin <lenghonglin@axera-tech.com>

arm64: dts: axera: add AX650 Demo initial support

This commit adds initial device tree support for the Axera AX650 SoC and
Demo board.

> diff --git a/arch/arm64/boot/dts/axera/ax650.dtsi b/arch/arm64/boot/dts/axera/ax650.dtsi
> new file mode 100644
> index 0000000000000..4fceaee81496c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axera/ax650.dtsi
> @@ -0,0 +1,134 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2026 Axera Semiconductor Co., Ltd.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;

[Severity: Medium]
Should this node use #address-cells = <2>? ARM64 systems typically require
2 cells to correctly represent the 64-bit MPIDR_EL1 register (which includes
the Aff3 field) and comply with ARM CPU device tree binding schemas.

> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a55";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +		};

[ ... ]

> +	/* GIC-400 block base; register frames start at offset 0x1000. */
> +	gic: interrupt-controller@4900000 {
> +		compatible = "arm,gic-400";

[Severity: High]
Can a legacy GIC-400 interrupt controller be paired with the Cortex-A55
cores defined above? Cortex-A55 cores integrate a GICv3 CPU interface
accessed via system registers and do not support the legacy GICv2
memory-mapped CPU interface (GICC).

The kernel will attempt to probe a GIC-400 and memory-map its GICC region,
while the CPUs expect to use GICv3 system registers, which could lead to
incorrect interrupt routing or boot failure.

[Severity: Medium]
Is the configuration of this node completely accurate?

The unit address (@4900000) does not match the first register address
(0x4901000).

The CPU interface size (second reg entry) appears to be 0x1000 instead of
0x2000. This undersized CPU interface prevents the kernel from accessing the
GICC_DIR register, forcing it to disable split-EOI functionality.

Does this node also need an interrupts property for the VGIC maintenance
interrupt? Without it, KVM virtualization will fail to initialize.

> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +		interrupt-controller;
> +		reg = <0x0 0x4901000 0x0 0x1000>,
> +			<0x0 0x4902000 0x0 0x1000>,
> +			<0x0 0x4904000 0x0 0x2000>,
> +			<0x0 0x4906000 0x0 0x2000>;
> +	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260821-ax650-v1-v1-0-e1b013938e6b@axera-tech.com?part=5