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From: sashiko-bot@kernel.org
To: "Santhosh Kumar K" <s-k6@ti.com>
Cc: "Vignesh Raghavendra" <vigneshr@ti.com>,
	devicetree@vger.kernel.org,
	"Takahiro Kuwano" <takahiro.kuwano@infineon.com>,
	"Miquel Raynal" <miquel.raynal@bootlin.com>,
	"Pratyush Yadav" <pratyush@kernel.org>,
	"Richard Weinberger" <richard@nod.at>,
	conor+dt@kernel.org, robh@kernel.org,
	"Michael Walle" <mwalle@kernel.org>
Subject: Re: [PATCH v8 03/18] spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz
Date: Fri, 21 Aug 2026 12:12:09 +0000	[thread overview]
Message-ID: <20260821121210.730DF1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260821114822.4040338-4-s-k6@ti.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] `spi->post_config_max_speed_hz` is not clamped against the controller's maximum supported speed (`spi->controller->max_speed_hz`).
- [Medium] `spi_new_ancillary_device()` does not copy `post_config_max_speed_hz` from the primary SPI device, breaking the feature for secondary chip selects.
--

--- Patch [3]: [PATCH v8 03/18] spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz ---
commit c2f1be0c2debf6f375fd36183b8ae8c58dccdc03
Author: Santhosh Kumar K <s-k6@ti.com>

spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz

Add post_config_max_speed_hz to struct spi_device and parse it from
the spi-max-post-config-frequency-hz DT property. This supports SPI
devices that operate at two distinct clock rates.

> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index 5b5b3bc5f0d8c..6b01ddb7cc324 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -2800,6 +2800,8 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
>  	/* Device speed */
>  	if (!of_property_read_u32(nc, "spi-max-frequency", &value))
>  		spi->max_speed_hz = value;
> +	if (!of_property_read_u32(nc, "spi-max-post-config-frequency-hz", &value))
> +		spi->post_config_max_speed_hz = value;

[Severity: Medium]
Does this new property also need to be clamped to the controller's maximum
supported speed?

In drivers/spi/spi.c:__spi_setup(), the pre-configuration speed is clamped:

__spi_setup() {
    ...
    if (spi->controller->max_speed_hz &&
        (!spi->max_speed_hz ||
         spi->max_speed_hz > spi->controller->max_speed_hz))
        spi->max_speed_hz = spi->controller->max_speed_hz;
    ...
}

Since post_config_max_speed_hz is not clamped here, could SPI-MEM request
an invalid post-configuration speed that the SPI controller physically
cannot support?

[ ... ]

> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> index 88d17fce02dcb..02fd602f29e8b 100644
> --- a/include/linux/spi/spi.h
> +++ b/include/linux/spi/spi.h

[ ... ]

> @@ -195,6 +197,7 @@ struct spi_device {
>  	struct device		dev;
>  	struct spi_controller	*controller;
>  	u32			max_speed_hz;
> +	u32			post_config_max_speed_hz;

[Severity: Medium]
Should this new field be copied to ancillary devices?

When creating secondary chip selects for multi-die packages,
drivers/spi/spi.c:spi_new_ancillary_device() clones the main device properties:

spi_new_ancillary_device() {
    ...
    /* Take over SPI mode/speed from SPI main device */
    ancillary->max_speed_hz = spi->max_speed_hz;
    ancillary->mode = spi->mode;
    ...
}

If post_config_max_speed_hz is not copied here, will ancillary devices
have a value of 0 and silently fail to apply the higher speed during
PHY tuning?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260821114822.4040338-1-s-k6@ti.com?part=3

  reply	other threads:[~2026-08-21 12:12 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-21 11:48 [PATCH v8 00/18] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-08-21 11:48 ` Santhosh Kumar K
2026-08-21 11:48 ` [PATCH v8 01/18] spi: dt-bindings: add spi-max-post-config-frequency-hz property Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 11:48 ` [PATCH v8 02/18] spi: dt-bindings: add spi-phy-pattern-partition property Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 11:48 ` [PATCH v8 03/18] spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 12:12   ` sashiko-bot [this message]
2026-08-21 11:48 ` [PATCH v8 04/18] spi: spi-mem: teach spi_mem_adjust_op_freq() about post-config ops Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 12:23   ` sashiko-bot
2026-08-21 11:48 ` [PATCH v8 05/18] spi: spi-mem: add execute_tuning callback and spi_mem_execute_tuning() Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 11:48 ` [PATCH v8 06/18] spi: cadence-quadspi: move cqspi_readdata_capture earlier Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 11:48 ` [PATCH v8 07/18] spi: cadence-quadspi: add DQS support to read data capture Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 11:48 ` [PATCH v8 08/18] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 12:54   ` sashiko-bot
2026-08-21 11:48 ` [PATCH v8 09/18] spi: cadence-quadspi: skip DDR PHY tuning for 2-byte-address ops (i2383) Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 11:48 ` [PATCH v8 10/18] spi: cadence-quadspi: refactor direct read path for PHY support Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 13:15   ` sashiko-bot
2026-08-21 11:48 ` [PATCH v8 11/18] spi: cadence-quadspi: enable PHY for direct reads Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 13:31   ` sashiko-bot
2026-08-21 11:48 ` [PATCH v8 12/18] spi: cadence-quadspi: enable PHY for indirect writes Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 13:43   ` sashiko-bot
2026-08-21 11:48 ` [PATCH v8 13/18] spi: cadence-quadspi: reprogram CS timing on every chip-select switch Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 11:48 ` [PATCH v8 14/18] spi: cadence-quadspi: reprogram PHY DLL on runtime resume Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 13:58   ` sashiko-bot
2026-08-21 11:48 ` [PATCH v8 15/18] mtd: spinand: extract variant ranking logic into spinand_op_find_best_variant() Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 11:48 ` [PATCH v8 16/18] mtd: spinand: negotiate optimal controller operating point before dirmap creation Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 14:13   ` sashiko-bot
2026-08-21 11:48 ` [PATCH v8 17/18] mtd: spi-nor: extract read op template construction into helper Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-21 11:48 ` [PATCH v8 18/18] mtd: spi-nor: run controller optimization before dirmap creation Santhosh Kumar K
2026-08-21 11:48   ` Santhosh Kumar K
2026-08-25  5:04 ` [PATCH v8 00/18] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-08-25  5:04   ` Santhosh Kumar K

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