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Fri, 21 Aug 2026 14:35:30 -0500 From: Alex Deucher To: CC: Philip Yang , Felix Kuehling , Alex Deucher Subject: [PATCH 32/95] drm/amdgpu: Add UALink NPA address layout helpers Date: Fri, 21 Aug 2026 15:33:55 -0400 Message-ID: <20260821193458.808626-33-alexander.deucher@amd.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260821193458.808626-1-alexander.deucher@amd.com> References: <20260821193458.808626-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD81:EE_|IA0PR12MB9048:EE_ X-MS-Office365-Filtering-Correlation-Id: bda7b859-38c3-4f38-506c-08deffbb5e48 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|23010399003|1800799024|376014|82310400026|36860700016|22082099003|18002099003|11063799006|56012099006|10067099003; X-Microsoft-Antispam-Message-Info: FR8/cIBJ8qyFDWzH/Mo3YfeBbvPzBFuXZuzUmzUJvN/rTb7fcbOp8vcTNltgabL07/QtKin6FhGYfNIN8MIlNXjKua482dZ7BBg/NsIJ+Bzbb3uaPCM/rKLa1Ye/8XICqqXXEPjAwhtjD5E0UCsK6I7XGta7E4B0JOuqjcGtxB+VxC2+zprkrF3PNbKixEZXzE41ecsNnUCMeBK+6mq2K24ViBAJen9f9zY558pb+8aKjjrN/1HzSWBkTM7rPSnTGUM+l7j9AN5rfFTWSDjVlOCTvEhJ8YnteK3T9HnTUA5YJKASOzPWd/kSTF7sXO5QOfz/UtsWk2mnznVUJiQOztf3eaU+uYjG8p+gDXc22LkoJyTPFTu26zLxV+RgRoJRFTs9gJ6EXPACzeR2IGjRWGTFG1tLQ2/BGYeNfuhpiyw/O2DL2upLjCHcv56Ary0wjBGoM19US6nBf53P5cG+THe3Fg5CleTdn8rBOPf0aCnGsONXvhqlTrSC0cOEEdt9CRZKzz8fwyzgu/rMD35mBlQBrJcVN9wjNzKSchn6wji/ighQZoXE90ccNmf9BJosZzQaHPw9OjH+f9XDqgvLXmDVUjHHf7lYupfb5LIMclUw3DApZGZgFeAblgbvEMnvNv+Hnmm+r2CjmggCz06TIXPGDho02o/+/3T2ffjUL1HScAH631bJvaxgJuws0gfW9FuZlqZNl4OzPIn/tcZGHQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD81.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB9048 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Philip Yang Add accessors for the local accelerator ID, addressing mode, and active peer bitmap, plus a TLB flush helper for the NPA VM. Provide per-ring size and byte offset helpers for both source-identification and source-alias addressing modes. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c | 101 +++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c index 511360335ed99..44abdf5511417 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c @@ -1335,3 +1335,104 @@ struct amdgpu_ualink_remote { struct amdgpu_ualink_peer peer[AMDGPU_UALINK_ACCEL_MAX]; }; +static inline struct amdgpu_ualink_remote *to_remote(struct amdgpu_device *adev) +{ + return adev->ualink.remote; +} + +static inline u32 ualink_accel_id(struct amdgpu_device *adev) +{ + return adev->ualink.info->ppod.accel_id; +} + +static inline enum amdgpu_ualink_addr_mode ualink_addr_mode(struct amdgpu_device *adev) +{ + return adev->ualink.info->vpod.addr_mode; +} + +/* + * address mode and NPA address for ring wptr, rptr, wb status, wb data + * + * source identification address mode + * + * we need to export different tail pointers for different remote GPU accel_id, + * hence we need to allocate a whole page for each remote GPU separately. + * + * rptr, wb data, status share the whole page with wptr. + * + * 1 page reserved NPA address for 1 active remote GPU, max 255 pages + * starting address: wptr NPA address + accel_id * 4K + * offset: + * remote interrupt ring wptr 0 + * remote shootdown ring wptr 8 + * remote interrupt wb status 16 + * remote interrupt wb data 20 + * remote interrupt ring rptr 24 + * remote shootdown wb status 32 + * remote shootdown wb data 36 + * remote shootdown ring rptr 40 + * + * source aliasing address mode + * + * wptr for different remote GPU can share same reserved 1 page NPA address page. + * + * to save reserved NPA address space, rptr, wb data, status for different + * remote GPU share same allocated 2 pages NPA address. + * + * 1 page reserved NPA address for wptr of all active remote GPUs + * offset: + * remote interrupt ring wptr accel_id * 16 + * remote shootdown ring wptr accel_id * 16 + 8 + * + * 2 page allocated NPA address for rptr, writeback of all active remote GPUs + * starting address: at accel_id * 32 for each remote GPU + * offset: + * remote interrupt wb status 0 + * remote interrupt wb data 4 + * remote interrupt ring rptr 8 + * remote shootdown wb status 16 + * remote shootdown wb data 20 + * remote shootdown ring rptr 24 + */ +static inline u32 ualink_wptr_size(struct amdgpu_device *adev) +{ + if (ualink_addr_mode(adev) == AMDGPU_UALINK_ADDR_MODE_SOURCE_IDENT) + return AMDGPU_GPU_PAGE_SIZE; + else + return 0; /* wptr uses the ring buffer for itself */ +} + +static inline u32 ualink_wb_size(struct amdgpu_device *adev) +{ + if (ualink_addr_mode(adev) == AMDGPU_UALINK_ADDR_MODE_SOURCE_IDENT) + return 0; /* share same page with wptr */ + else + return 2 * sizeof(struct amdgpu_ualink_wb); +} + +static inline u32 ualink_wptr_offset(struct amdgpu_device *adev, u32 accel_id) +{ + if (ualink_addr_mode(adev) == AMDGPU_UALINK_ADDR_MODE_SOURCE_IDENT) + return 0; /* one separate page per GPU */ + else + return accel_id * 2 * sizeof(u64); /* two pointers per GPU */ +} + +static inline u32 ualink_tlb_wptr_offset(struct amdgpu_device *adev, u32 accel_id) +{ + return ualink_wptr_offset(adev, accel_id) + sizeof(u64); +} + +static inline u32 ualink_wb_offset(struct amdgpu_device *adev, u32 accel_id) +{ + if (ualink_addr_mode(adev) == AMDGPU_UALINK_ADDR_MODE_SOURCE_IDENT) + return 2 * sizeof(u64); /* after two wptr pointers */ + else + return accel_id * ualink_wb_size(adev); +} + +static inline u32 ualink_tlb_wb_offset(struct amdgpu_device *adev, u32 accel_id) +{ + return ualink_wb_offset(adev, accel_id) + sizeof(struct amdgpu_ualink_wb); +} + -- 2.55.0