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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: H+3qhJH/xzPzkBw04GzR7Qiw8iIYEeQ6sOOvRCfNeC+qcRBpnCmf1RuKDQ7FRkNz0gxtXnycds8tjf3TmnJIDYZ/wzN79ZfPBhAvFY1PQcoe31jb/8bhEGepG7bX7hfrNxizuUPuU1H4xBlnzadlIg1bJJsw2XfIanwNptxDTiaTc49ah3fYuWZLCflc/xcxbtmYigsuyIV4z1nGZgS3OE55bAJV9OwZrI1nok5MIvwpRVkm3GSLFqfffibITvAwsHWySvui/9FlnQsj7PZn2HrmHImfi0WVAcmcjXQrzNNssi2dTAN4Q+nAvWQG4KGZAbc7ODP6pJmw5yboQzNeET3/d7ULtJsFmR8ocJjg8vkIW9pqyV+phEYRZUOYuln5jkcR3yd/eW3D6zSGxY8RhfTWJMH7d1BS2SG0KdyVurB59O2J1+mbme1rvkzgRxKP X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2026 19:35:59.5283 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 19fc7185-2358-4af0-b411-08deffbb6d97 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9181 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Philip Yang The UALink soft ring overflows under bursts of interrupts from remote GPUs. Size it at 16x the default soft ring to absorb the burst. While here, read the source accel_id and context dwords before the delegate path and log them, so the originating GPU is recorded for every interrupt. Signed-off-by: Philip Yang Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c | 17 ++++++++--------- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index 11f834c97d937..8d74a89b40cf8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -30,6 +30,7 @@ #define IH_RING_SIZE (256 * 1024) #define IH_SW_RING_SIZE (16 * 1024) /* enough for 512 CAM entries */ #define IH_PSP_RING_SIZE (SZ_4K) +#define IH_UALINK_RING_SIZE (256 * 1024) struct amdgpu_device; struct amdgpu_iv_entry; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c index dd45c2e20be0a..147a3744cccb9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c @@ -5353,13 +5353,6 @@ static int amdgpu_ualink_process_irq(struct amdgpu_device *adev, entry->ih == &adev->irq.ih ? "ring" : "ualink soft ring", entry->client_id, entry->src_id); - /* Copy IH entry into ualink soft ring. */ - if (entry->ih == &adev->irq.ih) { - dev_dbg(adev->dev, "delegate to ualink irq soft ring\n"); - amdgpu_irq_ualink_delegate(adev, entry, 8); - return handled; - } - /* ContextID 4 dwords */ src_acc_id = entry->pasid; dw0 = entry->src_data[0]; @@ -5367,8 +5360,14 @@ static int amdgpu_ualink_process_irq(struct amdgpu_device *adev, dw2 = entry->src_data[2]; dw3 = entry->src_data[3]; - dev_dbg(adev->dev, "src accel_id %u context id 0x%x 0x%x 0x%x 0x%x\n", - src_acc_id, dw0, dw1, dw2, dw3); + /* Copy IH entry into ualink soft ring. */ + if (entry->ih == &adev->irq.ih) { + dev_dbg(adev->dev, "src accel_id %u context id 0x%x 0x%x 0x%x 0x%x\n", + src_acc_id, dw0, dw1, dw2, dw3); + dev_dbg(adev->dev, "delegate to ualink irq soft ring\n"); + amdgpu_irq_ualink_delegate(adev, entry, 8); + return handled; + } msg_type = dw0 & AMDGPU_UALINK_MESSAGE_HEADER_MASK; local_acc_id = adev->ualink.info->ppod.accel_id; diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 7f4ef50195f6b..87f65fd3ed08a 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -638,7 +638,7 @@ static int ih_v7_0_sw_init(struct amdgpu_ip_block *ip_block) return r; dev_dbg(adev->dev, "ualink init ih_ualink\n"); - r = amdgpu_ih_ring_init(adev, &adev->irq.ih_ualink, sw_ring_size, true); + r = amdgpu_ih_ring_init(adev, &adev->irq.ih_ualink, IH_UALINK_RING_SIZE, true); if (r) return r; -- 2.55.0