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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499b915c6ccsm39410185e9.13.2026.08.21.13.36.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 13:36:50 -0700 (PDT) Date: Fri, 21 Aug 2026 21:36:46 +0100 From: David Laight To: James Cc: Raju Rangoju , Prashanth Kumar K R , netdev@vger.kernel.org, Thomas.Lendacky@amd.com, Simon Horman , Jakub Kicinski Subject: Re: [PATCH net v2] net: amd-xgbe: support receiving packets with bad FCS Message-ID: <20260821213646.7bbb94d6@pumpkin> In-Reply-To: <20260819091656.23943-1-aslan.jnn@gmail.com> References: <20260812091616.35811-1-aslan.jnn@gmail.com> <20260819091656.23943-1-aslan.jnn@gmail.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 19 Aug 2026 19:16:56 +1000 James wrote: > amd-xgbe driver currently sets the MAC_RCR.DCRCC bit whenever RX is > enabled. This disables hardware FCS validation, causing packets with > bad FCS to be accepted unconditionally. > > This change unsets DCRCC so that packets with bad FCS will be dropped, > in-line with typical behaviours of many other network controllers. > > Tests: > - Verified that packets with bad FCS are now dropped. > - Verified that receiving packets with bad FCS will increment the > `rx_crc_errors` counter. > > Signed-off-by: James Nugraha > --- > Changes in v2: > - Eliminated DCRCC toggling via RXALL: now it simply sets the > correct default value on MAC Rx enable > drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c > index 2de974213..3ceb130a0 100644 > --- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c > +++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c > @@ -3400,7 +3400,7 @@ static void xgbe_enable_rx(struct xgbe_prv_data *pdata) > XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); > > /* Enable MAC Rx */ > - XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); > + XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); > XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); > XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); > XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); > You can delete the line in the disable function that turns it off. But, really, you should be setting the required MAC_RCR bits in a single write. Doing RMW sequences on the hardware registers for each bit is really wrong. You also need to start with a known value for all the bits, otherwise 'silly' things can happen is (say) some bios boot code set bits you don't otherwise change. David