[PATCH 02/23] perf, perf/x86: Pass partition mask from KVM to perf/x86

[Zide Chen <zide.chen@intel.com>]

x86 PMU partitioning support requires mediated vPMU and is supported
only on Intel platforms. KVM is responsible for determining if PMU
partitioning can be enabled, and if so, it passes the mask to perf
core when creating a mediated PMU VM. The mask is host-wide state
shared by all mediated PMU guests.

Perf core passes the mask down to perf/x86 via the new callback
arch_perf_set_pmu_partition_mask(), which sanitizes it before applying
it to the newly added x86_pmu. The mask is cleared when the last
mediated PMU VM is released.

Note: PMU partitioning technically allows the host to run certain
!exclude_guest events while partitioned guests are running, as long as
such events don't use exclusive resources reserved for the guests. The
current behavior is kept: reject the creation of a partitioned guest
as long as any !exclude_guest host events exist.

Introduce PERF_PMU_CAP_PMU_PARTITION to indicate that the pmu supports
PMU partitioning. Note that virtualization of Intel PT and BTS is
currently unsupported; even if it were, this flag would not apply to
those PMUs, since their exclusive resources can't be shared between
host and guest, and their events are not subject to PMU partitioning
scheduling.

perf_create_mediated_pmu() is called with 0 for now; this will be
replaced with the actual partition_mask in a later patch.

Signed-off-by: Zide Chen <zide.chen@intel.com>
---
 arch/x86/events/core.c       | 58 ++++++++++++++++++++++++++++++++++++
 arch/x86/events/perf_event.h |  9 ++++++
 arch/x86/kvm/x86.c           |  2 +-
 include/linux/perf_event.h   |  4 ++-
 kernel/events/core.c         | 19 +++++++++---
 5 files changed, 86 insertions(+), 6 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 9b6df8bc9059..8032311c0a47 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2773,6 +2773,64 @@ static bool x86_pmu_filter(struct pmu *pmu, int cpu)
 	return ret;
 }
 
+/**
+ * arch_perf_set_pmu_partition_mask - Validate and set the VM-owned counter
+ *				      mask for mediated vPMU
+ * @partition_mask: Bitmask of PMU counters or other hardware resources
+ *		to hand over to mediated vPMU guests. 0 disables PMU
+ *		partitioning, as in the legacy model.
+ *
+ * Called via perf_create_mediated_pmu() to validate @partition_mask and,
+ * if valid, record it in x86_pmu.partition_mask for use by the
+ * scheduler, and set PERF_PMU_CAP_PMU_PARTITION on the generic PMU so
+ * perf core can check it without reaching into x86-private state.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+int arch_perf_set_pmu_partition_mask(u64 partition_mask)
+{
+	u64 current_mask = READ_ONCE(x86_pmu.partition_mask);
+	struct pmu *pmu;
+
+	/* Non-paritioned mediated guests fall into this case. */
+	if (current_mask == partition_mask)
+		return 0;
+
+	/*
+	 * AMD does not yet implement the hardware support for PMU partitioning
+	 * between host and guest. Thus limit it to Intel platforms with the
+	 * PerfMon masking VMX extension. Leave it to KVM to check the VMX
+	 * feature. KVM doesn't support vPMU on Hybrid CPUs at all.
+	 */
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || is_hybrid())
+		return -EOPNOTSUPP;
+
+	pmu = x86_get_pmu(raw_smp_processor_id());
+	if (!(pmu->capabilities & PERF_PMU_CAP_MEDIATED_VPMU))
+		return -EOPNOTSUPP;
+
+	/*
+	 * If a mediated-PMU VM was already created, the configured mask
+	 * cannot be changed.
+	 */
+	if (current_mask && partition_mask)
+		return -EINVAL;
+
+	/*
+	 * perf/core guarantees that this path is reached only after all
+	 * partitioned guests have been released.
+	 */
+	if (!partition_mask) {
+		WRITE_ONCE(x86_pmu.partition_mask, 0);
+		pmu->capabilities &= ~PERF_PMU_CAP_PMU_PARTITION;
+		return 0;
+	}
+
+	WRITE_ONCE(x86_pmu.partition_mask, partition_mask);
+	pmu->capabilities |= PERF_PMU_CAP_PMU_PARTITION;
+	return 0;
+}
+
 static struct pmu pmu = {
 	.pmu_enable		= x86_pmu_enable,
 	.pmu_disable		= x86_pmu_disable,
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index eae24bb35dc1..19beb16baa8e 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -883,6 +883,15 @@ struct x86_pmu {
 	int		events_mask_len;
 	int		apic;
 	u64		max_period;
+
+	/*
+	 * Bitmask of PMU resources that may be assigned to a guest.
+	 *
+	 * The mask is set when the first mediated vPMU is created and is
+	 * cleared when the last mediated vPMU is torn down.
+	 */
+	u64		partition_mask;
+
 	struct event_constraint *
 			(*get_event_constraints)(struct cpu_hw_events *cpuc,
 						 int idx,
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index d349224d2734..5f3215915c76 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -9328,7 +9328,7 @@ int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
 	if (enable_mediated_pmu && kvm->arch.enable_pmu &&
 	    !kvm->arch.created_mediated_pmu) {
 		if (irqchip_in_kernel(kvm)) {
-			r = perf_create_mediated_pmu();
+			r = perf_create_mediated_pmu(0);
 			if (r) {
 				pr_warn_ratelimited(PERF_MEDIATED_PMU_MSG);
 				return r;
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 48d851fbd8ea..bd952e09055d 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -306,6 +306,7 @@ struct perf_event_pmu_context;
 #define PERF_PMU_CAP_AUX_PAUSE		0x0200
 #define PERF_PMU_CAP_AUX_PREFER_LARGE	0x0400
 #define PERF_PMU_CAP_MEDIATED_VPMU	0x0800
+#define PERF_PMU_CAP_PMU_PARTITION	0x1000
 
 /**
  * pmu::scope
@@ -1931,10 +1932,11 @@ extern int perf_event_period(struct perf_event *event, u64 value);
 extern u64 perf_event_pause(struct perf_event *event, bool reset);
 
 #ifdef CONFIG_PERF_GUEST_MEDIATED_PMU
-int perf_create_mediated_pmu(void);
+int perf_create_mediated_pmu(u64 pmu_partition_mask);
 void perf_release_mediated_pmu(void);
 void perf_load_guest_context(void);
 void perf_put_guest_context(void);
+int arch_perf_set_pmu_partition_mask(u64 pmu_partition_mask);
 #endif
 
 #else /* !CONFIG_PERF_EVENTS: */
diff --git a/kernel/events/core.c b/kernel/events/core.c
index d7f3e2c2ecb1..9ce27cd83e04 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -6340,6 +6340,11 @@ static atomic_t nr_include_guest_events __read_mostly;
 static atomic_t nr_mediated_pmu_vms __read_mostly;
 static DEFINE_MUTEX(perf_mediated_pmu_mutex);
 
+int __weak arch_perf_set_pmu_partition_mask(u64 partition_mask)
+{
+	return partition_mask ? -EOPNOTSUPP : 0;
+}
+
 /* !exclude_guest event of PMU with PERF_PMU_CAP_MEDIATED_VPMU */
 static inline bool is_include_guest_event(struct perf_event *event)
 {
@@ -6387,15 +6392,18 @@ static void mediated_pmu_unaccount_event(struct perf_event *event)
  * No impact for the PMU without PERF_PMU_CAP_MEDIATED_VPMU. The perf
  * still owns all the PMU resources.
  */
-int perf_create_mediated_pmu(void)
+int perf_create_mediated_pmu(u64 partition_mask)
 {
-	if (atomic_inc_not_zero(&nr_mediated_pmu_vms))
-		return 0;
+	int ret;
 
 	guard(mutex)(&perf_mediated_pmu_mutex);
 	if (atomic_read(&nr_include_guest_events))
 		return -EBUSY;
 
+	ret = arch_perf_set_pmu_partition_mask(partition_mask);
+	if (ret)
+		return ret;
+
 	atomic_inc(&nr_mediated_pmu_vms);
 	return 0;
 }
@@ -6403,10 +6411,13 @@ EXPORT_SYMBOL_FOR_KVM(perf_create_mediated_pmu);
 
 void perf_release_mediated_pmu(void)
 {
+	guard(mutex)(&perf_mediated_pmu_mutex);
+
 	if (WARN_ON_ONCE(!atomic_read(&nr_mediated_pmu_vms)))
 		return;
 
-	atomic_dec(&nr_mediated_pmu_vms);
+	if (atomic_dec_and_test(&nr_mediated_pmu_vms))
+		arch_perf_set_pmu_partition_mask(0);
 }
 EXPORT_SYMBOL_FOR_KVM(perf_release_mediated_pmu);
 
-- 
2.55.0