Re: [PATCH v4 05/14] iio: adc: Add AD7768 and AD7768-4 core support

[Jonathan Cameron <jic23@kernel.org>]

On Fri, 21 Aug 2026 16:06:58 +0200
Janani Sunil <janani.sunil@analog.com> wrote:

> Add core support for the AD7768 and AD7768-4 simultaneous sampling ADCs.
> Configure supplies, clock and reset, use a custom regmap bus for the SPI
> protocol, and parse the enabled channels and input buffer settings from
> devicetree.
> 
> Connect the converter to an IIO backend for buffered capture with CRC,
> provide a fixed safe wideband sampling configuration and add runtime
> power management.
> 
> Signed-off-by: Janani Sunil <janani.sunil@analog.com>

One trivial thing from me. In general this is coming together nicely.


> diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c
> new file mode 100644
> index 000000000000..34233ad6cfca
> --- /dev/null
> +++ b/drivers/iio/adc/ad7768.c

> +static int ad7768_reset(struct ad7768_state *st)
> +{
> +	struct device *dev = regmap_get_device(st->regmap);
> +	struct reset_control *reset_ctrl;
> +	unsigned long reset_low_us;
> +	unsigned long mclk;
> +	int ret;
> +
> +	reset_ctrl = devm_reset_control_get_optional_exclusive(dev, NULL);
> +	if (IS_ERR(reset_ctrl))
> +		return PTR_ERR(reset_ctrl);
> +
> +	if (reset_ctrl) {
> +		mclk = clk_get_rate(st->mclk);
> +		if (!mclk)
> +			return -EINVAL;
> +
> +		/*
> +		 * Minimum RESET low pulse width: 2 x tMCLK
> +		 * (datasheet Table 1).
> +		 */
> +		reset_low_us = DIV_ROUND_UP_ULL(2ULL * USEC_PER_SEC, mclk);
> +
> +		ret = reset_control_assert(reset_ctrl);
> +		if (ret)
> +			return ret;
> +
> +		fsleep(max_t(unsigned long, 1, reset_low_us));

David covered this I think.  We should very rarely see the _t
variants in use in modern code.

> +
> +		ret = reset_control_deassert(reset_ctrl);
> +		if (ret)
> +			return ret;
> +	} else {
> +		ret = regmap_write(st->regmap, AD7768_REG_DATA_CONTROL,
> +				   AD7768_DATA_CONTROL_SPI_RESET_1);
> +		if (ret)
> +			return ret;
> +
> +		ret = regmap_write(st->regmap, AD7768_REG_DATA_CONTROL,
> +				   AD7768_DATA_CONTROL_SPI_RESET_2);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	/* ADC start-up time after reset: 1.66 ms max (datasheet Table 1) */
> +	fsleep(2000);

If it's 1.66 ms why not
	fsleep(1660);
?

> +
> +	return 0;
> +}