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Mon, 24 Aug 2026 01:14:14 -0700 (PDT) Received: from [127.0.1.1] ([209.170.101.129]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141860df25csm21408153c88.5.2026.08.24.01.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 01:14:12 -0700 (PDT) From: Eric Chung Subject: [PATCH 0/2] pinctrl: fix on Spacemit K1 SoC Date: Mon, 24 Aug 2026 16:13:58 +0800 Message-Id: <20260824-pinctrl-v1-0-e02ed7e9309f@riscstar.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAEb9i2oC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDCyMT3YLMvOSSohxdc0OLtFRTg9QkyzQLJaDqgqLUtMwKsEnRsRB+cWl SVmpyCUi7Um0tAKBQZ3FrAAAA X-Change-ID: 20260824-pinctrl-718fe50eb9f8 To: u-boot-spacemit@groups.io, u-boot@lists.u-boot-project.org, u-boot@lists.u-boot-project.org Cc: Tim Ouyang , Leo Liang , Yao Zi , Huan Zhou , Tom Rini , Eric Chung , Raymond Mao , Yixun Lan X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org - Add IO power domain control register programming via APBC block with ASAR unlocking for dual-voltage GPIO banks (3.3V/1.8V switching) - Fix drive strength configuration: use FIELD_PREP(), preserve io_type, return correct pin number, and remove redundant initialization Signed-off-by: Eric Chung --- Eric Chung (2): pinctrl: k1: fix drive strength configuration pinctrl: k1: add IO power domain configuration support drivers/pinctrl/spacemit/pinctrl-k1.c | 107 +++++++++++++++++++++++++++++++--- 1 file changed, 100 insertions(+), 7 deletions(-) --- base-commit: 6073c36b2c8d39afe3ecc789b281667a3ddebc70 change-id: 20260824-pinctrl-718fe50eb9f8 Best regards, -- Eric Chung