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Mon, 24 Aug 2026 01:14:22 -0700 (PDT) Received: from [127.0.1.1] ([209.170.101.129]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141860df25csm21408153c88.5.2026.08.24.01.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 01:14:21 -0700 (PDT) From: Eric Chung Date: Mon, 24 Aug 2026 16:14:00 +0800 Subject: [PATCH 2/2] pinctrl: k1: add IO power domain configuration support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260824-pinctrl-v1-2-e02ed7e9309f@riscstar.com> References: <20260824-pinctrl-v1-0-e02ed7e9309f@riscstar.com> In-Reply-To: <20260824-pinctrl-v1-0-e02ed7e9309f@riscstar.com> To: u-boot-spacemit@groups.io, u-boot@lists.u-boot-project.org, u-boot@lists.u-boot-project.org Cc: Tim Ouyang , Leo Liang , Yao Zi , Huan Zhou , Tom Rini , Eric Chung , Raymond Mao , Yixun Lan X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Dual-voltage GPIO banks default to 3.3V, but when externally supplied with 1.8V the internal logic must be explicitly reconfigured to match. Add the ability to program IO power domain control registers through the APBC block. These registers require unlocking the AIB Secure Access Register (ASAR) before every read/write, since configuring a 1.8V domain while 3.3V is externally supplied can cause back-powering and pin damage. Signed-off-by: Eric Chung Reviewed-by: Yao Zi --- drivers/pinctrl/spacemit/pinctrl-k1.c | 95 +++++++++++++++++++++++++++++++++-- 1 file changed, 92 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c index 6ed511879daf..ccfe26af310b 100644 --- a/drivers/pinctrl/spacemit/pinctrl-k1.c +++ b/drivers/pinctrl/spacemit/pinctrl-k1.c @@ -13,6 +13,7 @@ #include #include #include +#include /* * +---------+----------+-----------+--------+--------+----------+--------+ @@ -35,8 +36,23 @@ #define PAD_PULLUP BIT(14) #define PAD_PULL_EN BIT(15) -#define PIN_POWER_STATE_1V8 1800 -#define PIN_POWER_STATE_3V3 3300 +#define IO_PWR_DOMAIN_OFFSET 0x800 + +#define IO_PWR_DOMAIN_GPIO2_Kx 0x0c +#define IO_PWR_DOMAIN_GPIO3_K1 0x10 +#define IO_PWR_DOMAIN_MMC_Kx 0x1c +#define IO_PWR_DOMAIN_QSPI_K1 0x20 + +#define IO_PWR_DOMAIN_V18EN BIT(2) + +#define APBC_ASFAR 0x50 +#define APBC_ASSAR 0x54 + +#define APBC_ASFAR_AKEY 0xbaba +#define APBC_ASSAR_AKEY 0xeb10 + +#define PIN_POWER_STATE_1V8 1800 +#define PIN_POWER_STATE_3V3 3300 enum spacemit_pin_io_type { IO_TYPE_NONE = 0, @@ -61,12 +77,14 @@ struct spacemit_pinctrl_data { int (*get_pins)(struct udevice *dev); int (*get_functions)(struct udevice *dev); int (*get_io_type)(struct udevice *dev, unsigned int pin); + unsigned int (*pin_to_io_pd_offset)(unsigned int pin); }; struct spacemit_pinctrl_priv { void __iomem *regs; struct spacemit_pin_io *io_pins; int nr_io_pins; + struct regmap *regmap; }; struct spacemit_pin_mux_config { @@ -197,6 +215,28 @@ static int k1_get_io_type(struct udevice *dev, unsigned int selector) return -EINVAL; } +static unsigned int spacemit_k1_pin_to_io_pd_offset(unsigned int pin) +{ + unsigned int offset = 0; + + switch (pin) { + case 47 ... 52: + offset = IO_PWR_DOMAIN_GPIO3_K1; + break; + case 75 ... 80: + offset = IO_PWR_DOMAIN_GPIO2_Kx; + break; + case 98 ... 103: + offset = IO_PWR_DOMAIN_QSPI_K1; + break; + case 104 ... 109: + offset = IO_PWR_DOMAIN_MMC_Kx; + break; + } + + return offset; +} + /* use IO high level output current as the table */ static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = { { 0, 11 }, @@ -403,6 +443,35 @@ static const struct pinconf_param spacemit_pinconf_params[] = { { "power-source", PIN_CONFIG_POWER_SOURCE, U32_MAX }, }; +static void spacemit_set_io_power_domain(struct udevice *dev, + unsigned int pin, + unsigned int io_type) +{ + struct spacemit_pinctrl_priv *priv = dev_get_priv(dev); + struct spacemit_pinctrl_data *data; + unsigned int offset; + u32 val = 0; + + if (!priv->regmap) + return; + + data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev); + if (!data || !data->pin_to_io_pd_offset) + return; + + offset = data->pin_to_io_pd_offset(pin); + if (!offset) + return; + + if (io_type == IO_TYPE_1V8) + val = IO_PWR_DOMAIN_V18EN; + + regmap_write(priv->regmap, APBC_ASFAR, APBC_ASFAR_AKEY); + regmap_write(priv->regmap, APBC_ASSAR, APBC_ASSAR_AKEY); + + writel(val, priv->regs + IO_PWR_DOMAIN_OFFSET + offset); +} + static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector, unsigned int param, unsigned int argument) { @@ -418,6 +487,7 @@ static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector, data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev); if (!data || !data->pin_to_reg) return -EINVAL; + addr = data->pin_to_reg(dev, pin_selector); switch (param) { case PIN_CONFIG_BIAS_DISABLE: @@ -460,10 +530,14 @@ static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector, } break; } - if (!found && argument != PIN_POWER_STATE_1V8) { + if (!found && argument != PIN_POWER_STATE_1V8 && + argument != PIN_POWER_STATE_3V3) { dev_err(dev, "Invalid power source (%d)\n", argument); return -EINVAL; } + if (found) + spacemit_set_io_power_domain(dev, pin_selector, + priv->io_pins[i].io_type); break; default: return -EOPNOTSUPP; @@ -476,6 +550,7 @@ static int spacemit_pinctrl_probe(struct udevice *dev) struct spacemit_pinctrl_data *data; struct spacemit_pinctrl_priv *priv; struct clk_bulk clks; + struct ofnode_phandle_args args; size_t size; int ret; @@ -493,6 +568,19 @@ static int spacemit_pinctrl_probe(struct udevice *dev) dev_err(dev, "Fail to allocate memory\n"); return -ENOMEM; } + ret = dev_read_phandle_with_args(dev, "spacemit,apbc", + NULL, 0, 0, &args); + if (ret) { + dev_warn(dev, "no APBC phandle found, disable IO power domain switching\n"); + priv->regmap = NULL; + } else { + ret = regmap_init_mem(args.node, &priv->regmap); + if (ret) { + dev_warn(dev, "failed to get APBC regmap," + " disable IO power domain switching\n"); + priv->regmap = NULL; + } + } ret = clk_get_bulk(dev, &clks); if (ret) { @@ -520,6 +608,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { .get_pins = k1_get_pins, .get_functions = k1_get_functions, .get_io_type = k1_get_io_type, + .pin_to_io_pd_offset = spacemit_k1_pin_to_io_pd_offset, }; static const struct udevice_id spacemit_pinctrl_ids[] = { -- 2.51.0