[PATCH] irqchip/gic-v3: Remove the ISB between AP0Rn and AP1Rn

[Li Dou <li8d6kernel@163.com>]

ARM GICv3 specification says(in section 4.8.4 "System register access to
the Active Priorities registers"):

	an ISB is not required between each write to ICC_AP0R<n>_EL1,
	Secure ICC_AP1R<n>_EL1, and Non-secure ICC_AP1R<n>_EL1.

It means we can use one ISB after resetting AP0Rn and AP1Rn for context
synchronization. So just remove the previous one.

Signed-off-by: Li Dou <li8d6kernel@163.com>
---
 drivers/irqchip/irq-gic-v3.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 6e1fa5b247fc..3c48f46abb25 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1205,8 +1205,6 @@ static void gic_cpu_sys_reg_init(void)
 		case 4:
 			write_gicreg(0, ICC_AP0R0_EL1);
 		}
-
-		isb();
 	}
 
 	switch(pribits) {
-- 
2.43.0