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[89.217.29.191]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24967383e5sm1240049666b.45.2026.08.24.07.47.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 07:47:18 -0700 (PDT) From: Petr Belyaev To: amd-gfx@lists.freedesktop.org Cc: alexander.deucher@amd.com, timur.kristof@gmail.com, Petr Belyaev Subject: [PATCH] drm/amd/pm/smu7: Don't send VddC_Request on CI Date: Mon, 24 Aug 2026 16:47:14 +0200 Message-ID: <20260824144714.182835-1-upcfrost@gmail.com> X-Mailer: git-send-email 2.54.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Mon, 24 Aug 2026 15:22:53 +0000 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" smu7_upload_dpm_level_enable_mask() calls smu7_apply_minimum_dce_voltage_request() unconditionally, which sends PPSMC_MSG_VddC_Request to the SMC. CI SMC firmware does not implement that message: it is only defined in smu7_ppsmc.h, tonga_ppsmc.h and fiji_ppsmc.h, and there is no CI equivalent. The SMC therefore never writes SMC_RESP, PHM_WAIT_FIELD_UNEQUAL() spins until it gives up, and every call burns the full ~1.9s response timeout. Nothing downstream notices, because ci_send_msg_to_smc() returns 0 regardless of the outcome. The only effects are the delay and amdgpu: failed to send message 15f ret is 0 in dmesg. On a Radeon R7 260X (BONAIRE, 1002:6658) this is 40 messages per boot: 32 during the boot-time modeset, which becomes ~59s of blank screen, and 8 more on every DPMS wake, adding ~15s before the display comes back. Commit 0138610c1413 ("drm/amd/pm/smu7: Fix SMU7 voltage dependency on display clock") extended this feature to CI, which the previous implementation had deliberately excluded -- the old call site was guarded by pp_table_version == PP_TABLE_V1 with an adjacent comment reading "TO DO for v0 iceland and Ci". That commit was verified on a Radeon R9 M380, which is VI, so the CI path went untested. Restore the PP_TABLE_V1 condition. With it back the failed messages disappear entirely and both the boot modeset and the monitor wake are immediate. Fixes: 0138610c1413 ("drm/amd/pm/smu7: Fix SMU7 voltage dependency on display clock") Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/5678 Cc: stable@vger.kernel.org Signed-off-by: Petr Belyaev --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c index 6529a91..aadf6d5 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c @@ -3189,7 +3189,11 @@ static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - smu7_apply_minimum_dce_voltage_request(hwmgr); + /* CI SMC firmware does not implement PPSMC_MSG_VddC_Request, and each + * attempt costs a full SMC response timeout. + */ + if (hwmgr->pp_table_version == PP_TABLE_V1) + smu7_apply_minimum_dce_voltage_request(hwmgr); if (!data->sclk_dpm_key_disabled) { if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) -- 2.54.0 :wqa