Re: [PATCH 3/3] drm/xe/ggtt: invalidate engine GGTT TLBs for multi-queue GTs

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The newly introduced `xe_ggtt_invalidate_engine()` function hardcodes the primary GT for TLB invalidation, ignoring the media GT, which shares the same GGTT.
--

--- Patch [3]: [PATCH 3/3] drm/xe/ggtt: invalidate engine GGTT TLBs for multi-queue GTs ---
commit 167c9e87bd932fe22844ce91a7963cf6e1898546
Author: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

drm/xe/ggtt: invalidate engine GGTT TLBs for multi-queue GTs

This commit adds engine-side GGTT TLB invalidation during GGTT unmap
operations to ensure engines don't hit stale translations. The invalidation
is only issued if the GT has multi-queue engine classes.

> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 4cddd69f0e992..0f8946fddbaad 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c

[ ... ]

> @@ -612,6 +616,23 @@ static void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
>  	ggtt_invalidate_gt_tlb(ggtt->tile->media_gt);
>  }
>  
> +/*
> + * Drain engine-side GGTT TLBs on teardown so a recycled range's next
> + * occupant can't hit a predecessor's cached translation.
> + */
> +static void xe_ggtt_invalidate_engine(struct xe_ggtt *ggtt)
> +{
> +	struct xe_gt *gt = ggtt->tile->primary_gt;

[Severity: Medium]
Will this miss invalidating the engine TLBs on the media GT? 

If the media GT has multi-queue engine classes, hardcoding primary_gt here
seems like it would skip the media engines entirely, even though the GGTT
is shared across the entire tile. For comparison, xe_ggtt_invalidate() just
above invalidates both the primary and media GTs.

> +	int err;
> +
> +	if (!xe_gt_has_multi_queue(gt))
> +		return;
> +
> +	err = xe_tlb_inval_ggtt_full(&gt->tlb_inval);
> +	xe_gt_WARN(gt, err, "Failed to invalidate engine GGTT TLBs (%pe)",
> +		   ERR_PTR(err));
> +}

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Sashiko AI review · https://sashiko.dev/#/patchset/20260824163458.3129935-1-tilak.tirumalesh.tangudu@intel.com?part=3