From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2E0CC5DF81 for ; Mon, 24 Aug 2026 18:44:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F3E610E830; Mon, 24 Aug 2026 18:44:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="U3mKtVv+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id A795E10E82B for ; Mon, 24 Aug 2026 18:44:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787597098; x=1819133098; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HYaZyGKPCPKg1hRJXrad7S8BaBsHaR2pZ1RvFdnXZV4=; b=U3mKtVv+PDog33VwcqrmSt+eif9+1cqloaSHNimUvq571KUr6uRKCoON QeSlXdEMFizSUAThy7OD7BdmF85KnKO78ukKxz9dcvlapOpEFyknxnpyX XdbGGlI2kGtha4kvsmnfnWTIhAy5vP4QjJ+OTQn2MSqZd55j1TFaOGYfD TRb5ERBTZTz2mfSfRdAfLLpRx0sB5nwRo26cTODz/WJ4AlvxntCzlnjpU zpTpofPSIc0hC4JWHOT0kiVpgFGC5EdiL71Kubsg5kXp+srlz3hBCKj6r iW4S8l8tPmVTJYrKCi2nEo2YQ3gDpHcNXhI3bMattv40Vy7Czpt4THKdR A==; X-CSE-ConnectionGUID: d3Wdyb41QvO/JJDtxRYzvw== X-CSE-MsgGUID: ChPl8m0HQeSEVJSO9LJohw== X-IronPort-AV: E=McAfee;i="6800,10657,11885"; a="75592763" X-IronPort-AV: E=Sophos;i="6.25,241,1779174000"; d="scan'208";a="75592763" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2026 11:44:58 -0700 X-CSE-ConnectionGUID: hRrqXu36QFeqaMHm+UkoNw== X-CSE-MsgGUID: 1Yro9ZH5T7SPg492bPgC4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,241,1779174000"; d="scan'208";a="263351756" Received: from gfx-coremm-kmd15.iind.intel.com ([10.223.55.8]) by fmviesa010.fm.intel.com with ESMTP; 24 Aug 2026 11:44:57 -0700 From: Nareshkumar Gollakoti To: intel-xe@lists.freedesktop.org Cc: himal.prasad.ghimiray@intel.com, Nareshkumar Gollakoti Subject: [PATCH v2 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list Date: Tue, 25 Aug 2026 00:13:54 +0530 Message-ID: <20260824184356.1960708-6-naresh.kumar.g@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824184356.1960708-1-naresh.kumar.g@intel.com> References: <20260824184356.1960708-1-naresh.kumar.g@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Add ROW_INSTDONE_TDL_GFX, SS_LSC_HDC_IDLE_TDL_GFX and SLICE_ARB_STATUS register definitions and include them in the XeHPG extended GuC capture register list. v2:(Sashiko) - Refactored ROW_INSTDONE_TDL_GFX to ROW_INSTDONE_TDL_GFX - Add SLICE_ARB_STATUS register to xeHP register list - Refactor commit message Signed-off-by: Nareshkumar Gollakoti --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++++ drivers/gpu/drm/xe/xe_guc_capture.c | 5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 05542f20c7b5..b3ce7074f7d7 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -504,6 +504,8 @@ #define PAGE_FLTRPTQ_HEAD_GAMCTRL XE_REG(0xcf90) #define PAGE_FLTRPTQ_TAIL_GAMCTRL XE_REG(0xcf94) +#define SLICE_ARB_STATUS XE_REG_MCR(0xd814) + #define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED) #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0) @@ -568,6 +570,9 @@ #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534) #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31) +#define ROW_INSTDONE_TDL_GFX XE_REG_MCR(0xe580) +#define SS_LSC_HDC_IDLE_TDL_GFX XE_REG_MCR(0xe584) + #define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED) #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c index 324f25af3b0d..62832bd4af78 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.c +++ b/drivers/gpu/drm/xe/xe_guc_capture.c @@ -376,7 +376,10 @@ static const struct __ext_steer_reg xehpg_extregs[] = { {"SC_INSTDONE", XEHPG_SC_INSTDONE}, {"SC_INSTDONE_EXTRA", XEHPG_SC_INSTDONE_EXTRA}, {"SC_INSTDONE_EXTRA2", XEHPG_SC_INSTDONE_EXTRA2}, - {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT} + {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT}, + {"ROW_INSTDONE_TDL_GFX", ROW_INSTDONE_TDL_GFX}, + {"SS_LSC_HDC_IDLE_TDL_GFX", SS_LSC_HDC_IDLE_TDL_GFX}, + {"SLICE_ARB_STATUS", SLICE_ARB_STATUS} }; static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext, -- 2.43.0