All of lore.kernel.org
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Karthik Poosa" <karthik.poosa@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI
Date: Mon, 24 Aug 2026 18:56:33 +0000	[thread overview]
Message-ID: <20260824185633.A2C341F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260824184137.2164727-7-karthik.poosa@intel.com>

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Regression / Missing Initialization of vram_count disables MMIO sensors
- [Medium] Incomplete Implementation / Unexposed Hardware Monitoring Channels
- [Medium] Dead Code / Unreachable Feature for XE_CRESCENTISLAND (CRI) platforms
--

--- Patch [2]: [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI ---
commit dad00759fd95979bfa227e2bf51f1aad6c7133a4
Author: Karthik Poosa <karthik.poosa@intel.com>
Subject: drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI

This patch dynamically reads the number of VRAM temperature channels on
Crescent Island platforms. It increases the maximum channel count and uses
the pcode thermal config to determine available sensors.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index c15312b0858ca..8c8a519711230 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -39,7 +39,8 @@ enum xe_hwmon_reg_operation {
>  	REG_READ64,
>  };
>  
> -#define MAX_VRAM_CHANNELS      (16)
> +/* Maximum number of VRAM channels supported by Xe */
> +#define MAX_VRAM_CHANNELS      (80)

[Severity: Medium]
Will the hwmon subsystem actually expose these additional channels?

Looking at the hwmon_info array in xe_hwmon.c, it is statically defined
with exactly 21 temperature items, ending with a NULL terminator.
Because the hwmon core stops iterating at the terminator, sensors past
vram_ch_16 won't be queried or exported to sysfs, making this increase
to 80 ineffective.

[ ... ]

> @@ -786,6 +790,17 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  	drm_dbg(&hwmon->xe->drm, "thermal config count 0x%x\n", config);
>  	hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config);
>  
> +	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
> +		hwmon->temp.vram_count = REG_FIELD_GET(VRAM_COUNT_MASK, config);

[Severity: Medium]
Are the parsed VRAM channels accessible on Crescent Island platforms?

When is_vram_ch_available() runs, it calls xe_hwmon_get_reg() to get the
temperature register. However, xe_hwmon_get_reg() does not currently have
a branch for XE_CRESCENTISLAND in the REG_TEMP switch case.

Because it falls through and returns XE_REG(0), xe_reg_is_valid() will
fail in is_vram_ch_available(), making these newly parsed sensors
unreachable for CRI platforms.

> +		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS && hwmon->temp.vram_count) {
> +			drm_warn(&hwmon->xe->drm, "VRAM channel count %d exceeds max %d, clamping\n",
> +				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
> +			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
> +		}
> +	} else {
> +		hwmon->temp.vram_count = 16; /* For older platforms, max is 16 VRAM channels */
> +	}
> +
>  	return ret;
>  }

[ ... ]

> @@ -964,6 +979,9 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>  	u32 reg_val;
>  	u8 temp;
>  
> +	if (vram_id >= hwmon->temp.vram_count)
> +		return false;

[Severity: High]
Does this new check rely on pcode succeeding for older platforms?

If xe_hwmon_pcode_read_thermal_info() returns early due to a pcode mailbox
error when reading READ_THERMAL_LIMITS or READ_THERMAL_CONFIG, or is skipped
entirely, hwmon->temp.vram_count will remain 0.

Because of this check, an early return would unconditionally disable all
MMIO-based VRAM temperature sensors on platforms like BMG, losing existing
functionality. Previously, these sensors relied on a static maximum and
were completely decoupled from pcode initialization success.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824184137.2164727-1-karthik.poosa@intel.com?part=2

  reply	other threads:[~2026-08-24 18:56 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-24 18:41 [PATCH 0/3] drm/xe/hwmon: Update hwmon thermal mailbox handling Karthik Poosa
2026-08-24 18:41 ` [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors Karthik Poosa
2026-08-24 18:59   ` sashiko-bot
2026-08-25  6:45     ` Poosa, Karthik
2026-08-26 11:50   ` Nilawar, Badal
2026-08-27  5:16     ` Poosa, Karthik
2026-08-26 14:27   ` Raag Jadav
2026-08-26 20:20     ` Rodrigo Vivi
2026-09-02  7:48       ` Poosa, Karthik
2026-08-24 18:41 ` [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI Karthik Poosa
2026-08-24 18:57   ` sashiko-bot
2026-08-25  7:22     ` Poosa, Karthik
2026-08-26 12:31   ` Nilawar, Badal
2026-08-26 18:19   ` Raag Jadav
2026-08-26 20:10     ` Rodrigo Vivi
2026-09-02 15:25     ` Poosa, Karthik
2026-08-24 18:41 ` [PATCH 3/3] drm/xe/hwmon: Correct group selection for memory controller temperature Karthik Poosa
2026-08-24 18:54   ` sashiko-bot
2026-08-25  7:42     ` Poosa, Karthik
2026-08-24 18:41 ` [PATCH 0/3] drm/xe/hwmon: Update hwmon thermal mailbox handling Karthik Poosa
2026-08-24 18:41 ` [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors Karthik Poosa
2026-08-24 18:58   ` sashiko-bot
2026-08-24 18:41 ` [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI Karthik Poosa
2026-08-24 18:56   ` sashiko-bot [this message]
2026-08-24 18:41 ` [PATCH 3/3] drm/xe/hwmon: Correct group selection for memory controller temperature Karthik Poosa
2026-08-24 18:57   ` sashiko-bot
2026-08-24 23:02 ` ✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox handling Patchwork
2026-08-24 23:59 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-08-25  3:10 ` ✓ Xe.CI.FULL: success " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260824185633.A2C341F000E9@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=karthik.poosa@intel.com \
    --cc=sashiko-reviews@lists.linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.