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([85.233.101.104]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a59e025158sm11410217a12.11.2026.08.24.12.54.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 12:54:35 -0700 (PDT) From: Leander Kieweg To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Cc: airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, u.kleine-koenig@baylibre.com, Leander Kieweg Subject: [PATCH v3 1/2] dt-bindings: display: Add GlandaGPU binding Date: Mon, 24 Aug 2026 21:54:17 +0200 Message-ID: <20260824195418.17707-2-kieweg.leander@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824195418.17707-1-kieweg.leander@gmail.com> References: <20260824195418.17707-1-kieweg.leander@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add Device Tree binding documentation for GlandaGPU, a custom FPGA-based 2D display controller. For hardware designs and RTL sources, see: https://github.com/stiangglanda/GlandaGPU Signed-off-by: Leander Kieweg --- .../bindings/display/kieweg,gpu.yaml | 55 +++++++++++++++++++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + 2 files changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/kieweg,gpu.yaml diff --git a/Documentation/devicetree/bindings/display/kieweg,gpu.yaml b/Documentation/devicetree/bindings/display/kieweg,gpu.yaml new file mode 100644 index 000000000..c0fda8438 --- /dev/null +++ b/Documentation/devicetree/bindings/display/kieweg,gpu.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/kieweg,gpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GlandaGPU 2D Hardware Accelerated Display Controller + +maintainers: + - Leander Kieweg + +description: | + GlandaGPU is a custom FPGA soft-IP core providing a simple + 2D hardware-accelerated drawing engine with a VGA-compatible + display output. The register window covers a combined VRAM + MMIO + region, with MMIO registers at a fixed offset within it. + + For hardware designs and RTL sources, see: + https://github.com/stiangglanda/GlandaGPU + +properties: + compatible: + const: kieweg,gpu-1.0 + + reg: + maxItems: 1 + description: + Combined VRAM + MMIO register window (VRAM at offset 0, + MMIO registers at offset 0x00200000 within this range). + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: Bus and pixel clock provided to the FPGA IP. + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + + gpu@c0000000 { + compatible = "kieweg,gpu-1.0"; + reg = <0xc0000000 0x1000000>; + interrupt-parent = <&intc>; + interrupts = ; + clocks = <&osc1>; + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b1af9deac..fd2fd5ea2 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -666,6 +666,8 @@ patternProperties: description: Giantplus Technology Co., Ltd. "^gira,.*": description: Gira Giersiepen GmbH & Co. KG + "^kieweg,.*": + description: Leander Kieweg "^glinet,.*": description: GL Intelligence, Inc. "^globalscale,.*": -- 2.43.0