From: sashiko-bot@kernel.org
To: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>
Cc: linux-pci@vger.kernel.org, linux-cxl@vger.kernel.org
Subject: Re: [PATCH v2 13/13] PCI/CXL: Refuse an SBR of a CXL DPort unless authorized
Date: Tue, 25 Aug 2026 02:59:01 +0000 [thread overview]
Message-ID: <20260825025901.A93F11F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260825022628.3651434-14-fabio.m.de.francesco@linux.intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] cxl_sbr_unbind_regions() and cxl_sbr_enable_regions() ignore the return value of cxl_sbr_collect_regions().
--
--- Patch [13]: [PATCH v2 13/13] PCI/CXL: Refuse an SBR of a CXL DPort unless authorized ---
commit 8a167a59c2870bad236e079ff1641933532c8a30
Author: Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com>
PCI/CXL: Refuse an SBR of a CXL DPort unless authorized
This commit prevents the Secondary Bus Reset (SBR) bit from being
silently unmasked if it is left at the firmware default. It adds
cxl_sbr_allowed() to verify whether a CXL Downstream Port has its
Unmask SBR bit set, requiring explicit authorization otherwise.
> diff --git a/drivers/cxl/core/dport_sbr.c b/drivers/cxl/core/dport_sbr.c
> new file mode 100644
> index 0000000000000..823b63012f45b
> --- /dev/null
> +++ b/drivers/cxl/core/dport_sbr.c
[ ... ]
> +static void cxl_sbr_unbind_regions(struct pci_dev *dport_pci)
> +{
> + struct cxl_region *cxlr;
> + struct xarray regions;
> + unsigned long index;
> +
> + if (cxl_sbr_save_hdm_state(dport_pci))
> + pci_warn(dport_pci, "HDM state not saved, decode will not be restored\n");
> +
> + xa_init(®ions);
> +
> + cxl_sbr_collect_regions(dport_pci, ®ions);
[Severity: High]
Does this code silently ignore memory allocation failures during region
collection?
If xa_insert() in cxl_sbr_collect_regions() returns -ENOMEM under memory
pressure, the error appears to be ignored, resulting in a partial unbind
before a bus reset.
Could this leave uncollected regions bound while the link is reset, leading
to Machine Check Exceptions if the memory is accessed while still online?
> +
> + xa_for_each(®ions, index, cxlr)
> + cxl_region_unbind(cxlr);
> +
> + cxl_sbr_put_regions(®ions);
> +}
[ ... ]
> +static void cxl_sbr_enable_regions(struct pci_dev *dport_pci)
> +{
> + struct xarray *hdm_state;
> + struct cxl_region *cxlr;
> + struct xarray regions;
> + unsigned long index;
> +
> + xa_init(®ions);
> +
> + cxl_sbr_collect_regions(dport_pci, ®ions);
[Severity: High]
Is the return value of cxl_sbr_collect_regions() intentionally ignored here
as well?
If region collection fails, it seems the uncollected regions would skip the
enable step and permanently leak their disabled state.
> +
> + hdm_state = xa_load(&cxl_sbr_hdm_state, (unsigned long)dport_pci);
> + if (hdm_state)
> + cxl_sbr_recommit_decoders(dport_pci, hdm_state);
> + else
> + pci_warn(dport_pci, "no saved HDM state, decode not restored\n");
> +
> + xa_for_each(®ions, index, cxlr)
> + cxl_region_enable(cxlr);
> +
> + cxl_sbr_put_regions(®ions);
> + cxl_sbr_drop_hdm_state(dport_pci);
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260825022628.3651434-1-fabio.m.de.francesco@linux.intel.com?part=13
next prev parent reply other threads:[~2026-08-25 2:59 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 2:26 [PATCH v2 00/13] Make SBR work for CXL Downstream Ports Fabio M. De Francesco
2026-08-25 2:26 ` [PATCH v2 01/13] cxl/pci: Make the HDM and Mem_Enable writes callable from CXL Fabio M. De Francesco
2026-08-25 2:37 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 02/13] cxl/hdm: Add function to restore one HDM decoder Fabio M. De Francesco
2026-08-25 2:41 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 03/13] cxl/hdm: Add function to restore CXL.mem decode Fabio M. De Francesco
2026-08-25 2:45 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 04/13] cxl/hdm: Reprogram the HDM Decoders below a CXL Port Fabio M. De Francesco
2026-08-25 2:58 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 05/13] cxl/core: Restore the HDM decoders below DPort Fabio M. De Francesco
2026-08-25 2:43 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 06/13] drivers/base/memory: Add cxl_offline_memory() to offline a physical range Fabio M. De Francesco
2026-08-25 2:40 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 07/13] cxl/core: Add region disable and enable for a DPort SBR Fabio M. De Francesco
2026-08-25 2:44 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 08/13] cxl/core: Collect the regions routed through a DPort Fabio M. De Francesco
2026-08-25 2:41 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 09/13] PCI/CXL: Disable and re-enable CXL regions Fabio M. De Francesco
2026-08-25 2:39 ` sashiko-bot
2026-08-26 9:04 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 10/13] PCI/CXL: Clear ACS SV across an SBR of a CXL DPort Fabio M. De Francesco
2026-08-25 2:40 ` sashiko-bot
2026-08-26 8:47 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 11/13] PCI/DPC: Unbind regions for DPC recovery Fabio M. De Francesco
2026-08-25 2:51 ` sashiko-bot
2026-08-26 8:54 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 12/13] PCI/CXL: Add a sysfs entry to unmask SBR Fabio M. De Francesco
2026-08-25 2:51 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 13/13] PCI/CXL: Refuse an SBR of a CXL DPort unless authorized Fabio M. De Francesco
2026-08-25 2:59 ` sashiko-bot [this message]
2026-08-26 9:21 ` [PATCH v2 00/13] Make SBR work for CXL Downstream Ports Richard Cheng
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