Re: [PATCH v1 1/1] ARM: dts: draeger: Add devicetree files for M48 Intel/Altera SoCFPGA Cyclone

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
- [Low] Invalid and undocumented root compatible string.
- [Low] Leading `0x` in node unit-addresses.
- [Low] Undocumented transmit data skew properties (`txd*-skew-ps`) in GMAC node.
- [Low] Invalid and incomplete compatible string for SPI NOR flash.
- [Low] Usage of undocumented and obsolete properties (`cdns,page-size`, `cdns,block-size`, `m25p,fast-read`) in the SPI NOR flash node.
- [Low] Undocumented `bank-name` property in dw-apb-gpio port nodes.
--

--- Patch [1]: [PATCH v1 1/1] ARM: dts: draeger: Add devicetree files for M48 Intel/Altera SoCFPGA Cyclone ---
commit e3e6bb83ed93fbcc4abe100ece757b6cae933f06
Author: Petko Manolov <petko.manolov@konsulko.com>

ARM: dts: draeger: Add devicetree files for M48 Intel/Altera SoCFPGA Cyclone

This commit adds the DeviceTree source for the Draeger M48 Cyclone V SoC.
It configures basic SoC nodes, including memory, GPIO controllers, gigabit 
ethernet, i2c eeprom, and QSPI flash.

> --- /dev/null
> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> @@ -0,0 +1,132 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + *  (C) Copyright 2020 Draeger and Licensors, info@draeger.com
> + */
> +#include "socfpga_cyclone5.dtsi"
> +
> +/ {
> +	model = "Draeger M48 Cyclone V SoC";
> +	compatible = "draeger,M48/socfpga", "altr,socfpga-cyclone5", "altr,socfpga";

[Severity: Low]
Is this root compatible string correct? The DeviceTree specification does not
allow slashes in compatible strings, so "draeger,M48/socfpga" will trigger
warnings. Additionally, does the "draeger" vendor prefix need to be added
to vendor-prefixes.yaml, and this board compatible to the altera bindings?

[ ... ]
> +	soc {
> +		gpio3: gpio@0xff202000 {

[Severity: Low]
Should this unit-address omit the leading 0x? The DeviceTree specification
requires unit-addresses to be formatted as bare hex strings without the
0x prefix (e.g., gpio@ff202000).

> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0xff202000 0x20>;
> +			status = "okay";
> +
> +			portd: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				snps,nr-gpios = <2>;
> +				reg = <0>;
> +				bank-name = "SYNC_I";

[Severity: Low]
Is bank-name a valid property for these dw-apb-gpio port nodes? It does not
appear in the snps,dw-apb-gpio.yaml binding, which enforces
additionalProperties: false and will fail schema validation.

> +			};
> +		};
> +
> +		gpio4: gpio@0xff202020 {

[Severity: Low]
Similarly, should this node be named gpio@ff202020 to avoid the leading 0x
validation warnings?

> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0xff202020 0x20>;
> +			status = "okay";
> +
> +			porte: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				snps,nr-gpios = <2>;
> +				reg = <0>;
> +				bank-name = "SYNC_O";

[Severity: Low]
Does this bank-name property also need to be removed or documented to pass
dtbs_check?

[ ... ]
> +&gmac0 {
> +	status = "okay";
> +	phy-mode = "rgmii-id";
> +	rxc-skew-ps = <1860>;
> +	rxd0-skew-ps = <0>;
> +	rxd1-skew-ps = <0>;
> +	rxd2-skew-ps = <0>;
> +	rxd3-skew-ps = <0>;
> +	rxdv-skew-ps = <0>;
> +	txc-skew-ps = <900>;
> +	txd0-skew-ps = <0>;
> +	txd1-skew-ps = <0>;
> +	txd2-skew-ps = <0>;
> +	txd3-skew-ps = <0>;

[Severity: Low]
Are these txd0 through txd3 skew properties supported by the stmmac schema?
While RX skews and txc-skew-ps are documented, the txd[0-3]-skew-ps properties
are missing from altr,socfpga-stmmac.yaml, which will cause validation to fail
since unevaluatedProperties is set to false.

[ ... ]
> +&qspi {
> +	status = "okay";
> +
> +	flash0: n25q00@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "n25q00";

[Severity: Low]
Could this compatible string be incomplete? Standard OF-based driver matching
and the mtd/jedec,spi-nor.yaml binding require a vendor prefix and the generic
fallback, such as "micron,n25q00", "jedec,spi-nor".

> +		reg = <0>;
> +
> +		/* chip select */
> +		spi-max-frequency = <100000000>;
> +		m25p,fast-read;
> +		cdns,page-size = <256>;
> +		cdns,block-size = <16>;

[Severity: Low]
Are these properties correct for modern Cadence QSPI bindings?
The cdns,page-size and cdns,block-size properties are undocumented, and
m25p,fast-read is an obsolete property not present in modern schemas. They
will trigger dtbs_check validation errors.

> +		cdns,read-delay = <4>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825140225.3968019-2-petko.manolov@konsulko.com?part=1