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Ip=[149.199.90.133]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C6191.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7166 Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=Benjamin.Cheatham@amd.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org v2 Changes: - Remove SRSO_NO bit (not supported on release hardware) - Rebase on master (fd7ab698c921e2e97aa1b1d5b719d42103a2dd58) This series adds support for AMD's upcoming EPYC Zen 6 CPU models (EPYC-Venice). The first four patches add support for the EPYC-Venice model while the last patch adds the actual model. The EPYC-Venice model is based on the EPYC-Turin model feature set with the following feature additions: ERAPS, TSC Adjustment, and Shadow Stack and support for the following instructions: AVX512 FP16, AVX512 IFMA, AVX NE-Convert, AVX VNNI Int8, and AVX512 BMM instructions as well as new cache values. Some of these features (ERAPS) were only just recently merged into the Linux kernel. It's recommended to use a v7.0+ kernel to leverage the full support of the model. Amit Shah (1): target/i386: Add getting RAPSIZE for ERAPS enabled guests Ben Cheatham (2): target/i386: Update RAPSIZE definition target/i386: Add EPYC-Venice CPU model Nikunj A Dadhania (1): target/i386: Add AVX512 Bit Matrix Multiply (BMM) support target/i386/cpu.c | 151 +++++++++++++++++++++++++++++++++++++++++++++- target/i386/cpu.h | 9 ++- 2 files changed, 155 insertions(+), 5 deletions(-) -- 2.53.0