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envelope-from=amachhiw@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2026/08/26 04:58 PM, Amit Machhiwal wrote: > On 2026/08/26 10:38 AM, Chinmay Rath wrote: > > From: "Mukesh Kumar Chaurasiya (IBM)" > > > > Instructions converted: > > > > - slw > > - srw Also, the commit log could be improved: Move slw and srw to decodetree specification using the @X_rc format. The existing shift-masking logic from gen_slw/gen_srw is preserved verbatim in the new trans_SLW/trans_SRW handlers. > > > > Signed-off-by: Mukesh Kumar Chaurasiya (IBM) > > Reviewed-by: Glenn Miles > > Signed-off-by: Chinmay Rath > > --- > > target/ppc/insn32.decode | 6 +++ > > target/ppc/translate.c | 49 ---------------------- > > target/ppc/translate/fixedpoint-impl.c.inc | 48 +++++++++++++++++++++ > > 3 files changed, 54 insertions(+), 49 deletions(-) > > > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > > index 701c66b347..66d2f455a9 100644 > > --- a/target/ppc/insn32.decode > > +++ b/target/ppc/insn32.decode > > @@ -505,6 +505,12 @@ HASHCHK 011111 ..... ..... ..... 1011110010 . @X_DW > > HASHSTP 011111 ..... ..... ..... 1010010010 . @X_DW > > HASHCHKP 011111 ..... ..... ..... 1010110010 . @X_DW > > > > +# Fixed-Point Shift Instructions > > + > > +SLW 011111 ..... ..... ..... 0000011000 . @X_rc > > +SRW 011111 ..... ..... ..... 1000011000 . @X_rc > > + > > + > > Nit: this looks like an extra blank line - can be removed. Otherwise, > > Reviewed-by: Amit Machhiwal > > > ## BCD Assist > > > > ADDG6S 011111 ..... ..... ..... - 001001010 - @X > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > > index ee14fbfd96..f2b7505634 100644 > > --- a/target/ppc/translate.c > > +++ b/target/ppc/translate.c > > @@ -2315,29 +2315,6 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06); > > > > /*** Integer shift ***/ > > > > -/* slw & slw. */ > > -static void gen_slw(DisasContext *ctx) > > -{ > > - TCGv t0, t1; > > - > > - t0 = tcg_temp_new(); > > - /* AND rS with a mask that is 0 when rB >= 0x20 */ > > -#if defined(TARGET_PPC64) > > - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); > > - tcg_gen_sari_tl(t0, t0, 0x3f); > > -#else > > - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); > > - tcg_gen_sari_tl(t0, t0, 0x1f); > > -#endif > > - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); > > - t1 = tcg_temp_new(); > > - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); > > - tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); > > - tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); > > - if (unlikely(Rc(ctx->opcode) != 0)) { > > - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); > > - } > > -} > > > > /* sraw & sraw. */ > > static void gen_sraw(DisasContext *ctx) > > @@ -2379,30 +2356,6 @@ static void gen_srawi(DisasContext *ctx) > > } > > } > > > > -/* srw & srw. */ > > -static void gen_srw(DisasContext *ctx) > > -{ > > - TCGv t0, t1; > > - > > - t0 = tcg_temp_new(); > > - /* AND rS with a mask that is 0 when rB >= 0x20 */ > > -#if defined(TARGET_PPC64) > > - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); > > - tcg_gen_sari_tl(t0, t0, 0x3f); > > -#else > > - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); > > - tcg_gen_sari_tl(t0, t0, 0x1f); > > -#endif > > - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); > > - tcg_gen_ext32u_tl(t0, t0); > > - t1 = tcg_temp_new(); > > - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); > > - tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); > > - if (unlikely(Rc(ctx->opcode) != 0)) { > > - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); > > - } > > -} > > - > > #if defined(TARGET_PPC64) > > /* sld & sld. */ > > static void gen_sld(DisasContext *ctx) > > @@ -5777,10 +5730,8 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), > > GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), > > GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), > > GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), > > -GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), > > GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), > > GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), > > -GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), > > #if defined(TARGET_PPC64) > > GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), > > GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), > > diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc > > index 91f9c6c391..9d04b96316 100644 > > --- a/target/ppc/translate/fixedpoint-impl.c.inc > > +++ b/target/ppc/translate/fixedpoint-impl.c.inc > > @@ -1406,3 +1406,51 @@ TRANS(HASHST, do_hash, false, gen_helper_HASHST) > > TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK) > > TRANS(HASHSTP, do_hash, true, gen_helper_HASHSTP) > > TRANS(HASHCHKP, do_hash, true, gen_helper_HASHCHKP) > > + > > +static bool trans_SLW(DisasContext *ctx, arg_SLW *a) > > +{ > > + TCGv t0, t1; > > + > > + t0 = tcg_temp_new(); > > + /* AND rt with a mask that is 0 when rB >= 0x20 */ > > +#if defined(TARGET_PPC64) > > + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x3a); > > + tcg_gen_sari_tl(t0, t0, 0x3f); > > +#else > > + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x1a); > > + tcg_gen_sari_tl(t0, t0, 0x1f); > > +#endif > > + tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0); > > + t1 = tcg_temp_new(); > > + tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x1f); > > + tcg_gen_shl_tl(cpu_gpr[a->ra], t0, t1); > > + tcg_gen_ext32u_tl(cpu_gpr[a->ra], cpu_gpr[a->ra]); > > + if (unlikely(a->rc)) { > > + gen_set_Rc0(ctx, cpu_gpr[a->ra]); > > + } > > + return true; > > +} > > + > > +static bool trans_SRW(DisasContext *ctx, arg_SRW *a) > > +{ > > + TCGv t0, t1; > > + > > + t0 = tcg_temp_new(); > > + /* AND rt with a mask that is 0 when rB >= 0x20 */ > > +#if defined(TARGET_PPC64) > > + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x3a); > > + tcg_gen_sari_tl(t0, t0, 0x3f); > > +#else > > + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x1a); > > + tcg_gen_sari_tl(t0, t0, 0x1f); > > +#endif > > + tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0); > > + tcg_gen_ext32u_tl(t0, t0); > > + t1 = tcg_temp_new(); > > + tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x1f); > > + tcg_gen_shr_tl(cpu_gpr[a->ra], t0, t1); > > + if (unlikely(a->rc)) { > > + gen_set_Rc0(ctx, cpu_gpr[a->ra]); > > + } > > + return true; > > +} > > -- > > 2.55.0 > >