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envelope-from=amachhiw@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2026/08/26 10:38 AM, Chinmay Rath wrote: > From: Shivang Upadhyay > > Move below instructions to decodetree specification : > > cr{and, or, xor, nand, nor, eqv, andc, orc} : XL-form > > The changes were verified by validating that the tcg ops generated by > those instructions remain the same, which were captured with the '-d > in_asm,op' flag. > > Signed-off-by: Shivang Upadhyay > Reviewed-by: Glenn Miles > Signed-off-by: Chinmay Rath > --- > target/ppc/insn32.decode | 11 ++++ > target/ppc/translate.c | 59 ---------------------- > target/ppc/translate/fixedpoint-impl.c.inc | 45 +++++++++++++++++ > 3 files changed, 56 insertions(+), 59 deletions(-) > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index dc708b5442..a3973e042d 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -516,6 +516,17 @@ CFUGED 011111 ..... ..... ..... 0011011100 - @X > PDEPD 011111 ..... ..... ..... 0010011100 - @X > PEXTD 011111 ..... ..... ..... 0010111100 - @X > > +## Condition Register Instructions > + > +CRAND 010011 ..... ..... ..... 0100000001 - @X > +CROR 010011 ..... ..... ..... 0111000001 - @X > +CRNAND 010011 ..... ..... ..... 0011100001 - @X > +CRXOR 010011 ..... ..... ..... 0011000001 - @X > +CRNOR 010011 ..... ..... ..... 0000100001 - @X > +CREQV 010011 ..... ..... ..... 0100100001 - @X > +CRANDC 010011 ..... ..... ..... 0010000001 - @X > +CRORC 010011 ..... ..... ..... 0110100001 - @X > + > # Fixed-Point Hash Instructions > > HASHST 011111 ..... ..... ..... 1011010010 . @X_DW > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index d01981de73..5b08d9b282 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -2920,53 +2920,6 @@ static inline void gen_setlr(DisasContext *ctx, target_ulong nip) > tcg_gen_movi_tl(cpu_lr, nip); > } > > -/*** Condition register logical ***/ > -#define GEN_CRLOGIC(name, tcg_op, opc) \ > -static void glue(gen_, name)(DisasContext *ctx) \ > -{ \ > - uint8_t bitmask; \ > - int sh; \ > - TCGv_i32 t0, t1; \ > - sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ > - t0 = tcg_temp_new_i32(); \ > - if (sh > 0) \ > - tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ > - else if (sh < 0) \ > - tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ > - else \ > - tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ > - t1 = tcg_temp_new_i32(); \ > - sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ > - if (sh > 0) \ > - tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ > - else if (sh < 0) \ > - tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ > - else \ > - tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ > - tcg_op(t0, t0, t1); \ > - bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ > - tcg_gen_andi_i32(t0, t0, bitmask); \ > - tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ > - tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ > -} > - > -/* crand */ > -GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); > -/* crandc */ > -GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); > -/* creqv */ > -GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); > -/* crnand */ > -GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); > -/* crnor */ > -GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); > -/* cror */ > -GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); > -/* crorc */ > -GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); > -/* crxor */ > -GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); > - > /*** System linkage ***/ > > /* rfi (supervisor only) */ > @@ -5120,18 +5073,6 @@ GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) > GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) > #endif > > -#undef GEN_CRLOGIC > -#define GEN_CRLOGIC(name, tcg_op, opc) \ > -GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) > -GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), > -GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), > -GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), > -GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), > -GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), > -GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), > -GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), > -GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), > - > #undef GEN_MAC_HANDLER > #define GEN_MAC_HANDLER(name, opc2, opc3) \ > GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) > diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc > index d768a0454d..26b308e435 100644 > --- a/target/ppc/translate/fixedpoint-impl.c.inc > +++ b/target/ppc/translate/fixedpoint-impl.c.inc > @@ -540,6 +540,51 @@ static bool trans_MFCR(DisasContext *ctx, arg_MFCR *a) > return true; > } > > +static bool cr_logic_common(DisasContext *ctx, arg_X *a, > + void (*tcg_op)(TCGv_i32, TCGv_i32, TCGv_i32)) > +{ > + Extra new line - please remove it. > + uint8_t bitmask; > + int sh; > + TCGv_i32 t0, t1; > + sh = (a->rt & 0x03) - (a->ra & 0x03); > + t0 = tcg_temp_new_i32(); > + if (sh > 0) { > + tcg_gen_shri_i32(t0, cpu_crf[a->ra >> 2], sh); > + } else if (sh < 0) { > + tcg_gen_shli_i32(t0, cpu_crf[a->ra >> 2], -sh); > + } else { > + tcg_gen_mov_i32(t0, cpu_crf[a->ra >> 2]); > + } > + > + t1 = tcg_temp_new_i32(); It maybe a good idea to keep these allocations together, consistent with other places in this file. t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); ... With these nits fixed: Reviewed-by: Amit Machhiwal > + sh = (a->rt & 0x03) - (a->rb & 0x03); > + if (sh > 0) { > + tcg_gen_shri_i32(t1, cpu_crf[a->rb >> 2], sh); > + } else if (sh < 0) { > + tcg_gen_shli_i32(t1, cpu_crf[a->rb >> 2], -sh); > + } else { > + tcg_gen_mov_i32(t1, cpu_crf[a->rb >> 2]); > + } > + tcg_op(t0, t0, t1); > + > + bitmask = 0x08 >> (a->rt & 0x03); > + tcg_gen_andi_i32(t0, t0, bitmask); > + tcg_gen_andi_i32(t1, cpu_crf[a->rt >> 2], ~bitmask); > + tcg_gen_or_i32(cpu_crf[a->rt >> 2], t0, t1); > + > + return true; > +} > + > +TRANS(CRAND, cr_logic_common, tcg_gen_and_i32); > +TRANS(CROR, cr_logic_common, tcg_gen_or_i32); > +TRANS(CRXOR, cr_logic_common, tcg_gen_xor_i32); > +TRANS(CRNAND, cr_logic_common, tcg_gen_nand_i32); > +TRANS(CRNOR, cr_logic_common, tcg_gen_nor_i32); > +TRANS(CRANDC, cr_logic_common, tcg_gen_andc_i32); > +TRANS(CREQV, cr_logic_common, tcg_gen_eqv_i32); > +TRANS(CRORC, cr_logic_common, tcg_gen_orc_i32); > + > static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool compute_ca, > bool compute_ov, bool compute_rc0) > { > -- > 2.55.0 >