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Thu, 27 Aug 2026 09:51:39 -0700 (PDT) From: Michal Gorlas Date: Thu, 27 Aug 2026 18:51:00 +0200 Subject: [PATCH RESEND v2] PCI: imx6: Enable ASPM L1 only iff CLKREQ# is supported Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260827-l1-conditional-imx-v2-1-40b324aa2a94@9elements.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3161; i=michal.gorlas@9elements.com; h=from:subject:message-id; bh=Cv42epPoNORB5PcqX0k0Mx2zGd1B1jSGrLyDLj5cWzY=; b=owEBbQKS/ZANAwAKAWKaksyA3pPLAcsmYgBqkGsXl1XXO7CczlDW42hMAd4AcZI7L/miM5XQi 4HNMYkWKaiJAjMEAAEKAB0WIQTgoC0bQQLz7jVH2W9impLMgN6TywUCapBrFwAKCRBimpLMgN6T y4SzD/wJXnY4K3bTVEqMPYGKOQB6IFLjmxS3tCQvn8h7h8t5zTdtMDxOFbhTcZmNtsMWFM2KZ3b hGFQ41UMlczcyAe1IoHiRfx16B6MehkVhQYZaTR9Xc4yIhY4YPDHqMWll3BcRup8lRQDdeeU0z6 bcPDaS0n9KjobxN5WwaVucD/5Bz423OQstjwCKLJcDCiGTVKIfMZF7uD420M1SBbMJIvwLiZi/A j8d8OYr9+QTsNKsU6HWf86ylOYXSwl2dH1fzh5rWkfmJitWKAqq7keIyhA3kbrCyVA9fsivsWQ2 hOlnFLaXj7zbuKnsYSP1XJ3dlO5XtQ/Wnwt1/ZybSlFY5lVslsBm6Mssdn6ho8xejaRYHnH2/i7 bC5g08hPvdLX+E0VkiN07CNG2LIdmYK6gW7+ckVek5T+ddG3i6+Cb/YBB71y4wlqS6o0g++uKzE +HK4CPkHupuSyC2MapHS1fDejhDh8/ab/nETLOz+uZ7SEMXlnCoHuXeCbEuhK0pzeY7VSFVje6V JyHtOsXDPTxO7JTcbhWO4v6rdu6+HAlbkJ/Bl/56rJmxXQqP9g8eK+zd+tIBoqkr+rRZgA37Aa7 O0C3NOOnOWAKdeAMraI9QgkEix0O6xybs4nEcQSkUDsa33YGklAhit7mq0u2jBNjiK7Sa3NvDZz NwUnFbNbJkBgepw== X-Developer-Key: i=michal.gorlas@9elements.com; a=openpgp; fpr=B4EB74EA41969D1140A4D1791596726986433F8C Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms"), ASPM states are force enabled on all devicetree platforms. This causes PCI devices on some i.MX SoCs (for e.g. i.MX 8M Plus Kontron SMARC eval carrier) to enter L1 even though CLKREQ# is not supported (and consequently supports-clkreq is not set in pcie controller node of their DT), which causes the device to never wake up from L1. Hence, disable L1 capability in the LNKCAP register if supports-clkreq is not set in the DT explicitly. For devices that set IMX_PCIE_FLAG_BROKEN_SUSPEND, disable L1 on resume as well, as these skip imx_pcie_host_init(). Note, the logic here is very similar to 613f3255a35a, only difference is that leaving L0s enabled does not cause issues (at least I never encountered them myself when testing on the device) as its not dependent on CLKREQ# being physically there. Since there is already a way of specifying its presence in the DT, the driver should be aware and disable L1. Fixes: f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms") Signed-off-by: Michal Gorlas Tested-by: Richard Zhu Reviewed-by: Richard Zhu --- Changes in v2: - disable L1 unconditionally on resume for platforms advertising IMX_PCIE_FLAG_BROKEN_SUSPEND (Sashiko) - typos in the commit message - Link to v1: https://patch.msgid.link/20260719-l1-conditional-imx-v1-1-a55a57915c68@9elements.com --- drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 98e1db751132..1fdcbcd2422e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1318,6 +1318,22 @@ static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool assert) } } +static void imx_pcie_disable_l1(struct dw_pcie *pci) +{ + u32 val; + u8 offset; + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + dw_pcie_dbi_ro_wr_en(pci); + + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_ASPM_L1; + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); + + dw_pcie_dbi_ro_wr_dis(pci); +} + static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -1442,6 +1458,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) imx_setup_phy_mpll(imx_pcie); + if (!imx_pcie->supports_clkreq) + imx_pcie_disable_l1(pci); + return 0; err_phy_off: @@ -1748,6 +1767,7 @@ static int imx_pcie_resume_noirq(struct device *dev) return ret; imx_pcie_deassert_core_reset(imx_pcie); imx_pcie_assert_perst(imx_pcie, false); + imx_pcie_disable_l1(imx_pcie->pci); /* * Using PCIE_TEST_PD seems to disable MSI and powers down the --- base-commit: a13c140cc289c0b7b3770bce5b3ad42ab35074aa change-id: 20260713-l1-conditional-imx-c2bfd20ae085 Best regards, -- Michal Gorlas