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([180.150.112.50]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39670599275sm2210473a91.0.2026.08.26.22.10.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 22:10:11 -0700 (PDT) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini Cc: Peter Maydell , Weiwei Li , Liu Zhiwei , Chao Liu , Nicholas Piggin , Anirudh Srinivasan , Michael Ellerman , Portia Stephens , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Date: Thu, 27 Aug 2026 14:39:39 +0930 Message-ID: <20260827050953.67184-1-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=joel.stan@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org When testing Richard's TCG RVV changes I went down the rabbit hole that is tests/tcg/multiarch. Out the other side is this series, which enables the multiarch and record/replay tests for riscv64, and fixes the memory-sve aarch64 test while adding a memory-rvv test for riscv64. The first half of the series performs some housekeeping on the semihost tests and the softmmu makefile in tests/tcg/riscv64. The second half enables the multiarch tests, and looks at the vectorised memory.c test. The final patch adds a very coarse check for vectorisation by grepping objdump for vector loads and stores. Although it's not the neatest, it would have caught the regression in memory-sve, so it is worthwhile having in the tree. Joel Stanley (12): tests/tcg/riscv64: Include stdint.h in semicall.h tests/tcg/riscv64: Clean up semicall.h inline asm tests/tcg/riscv64: Boot semihost tests with -bios none -kernel tests/tcg/riscv64: Update semihosting linker script tests/tcg/riscv64: Rework rules for semihost tests tests/tcg/riscv64: Enable multiarch system tests tests/tcg/riscv64: Enable memory record and replay test tests/tcg/aarch64: Don't leak memory-sve CFLAGS tests/tcg/multiarch: Fix vectorisation of memory test tests/tcg/riscv64: Enable vectorised memory test configure: Provide OBJDUMP to the tcg tests tests/tcg: Check vector memory tests contain vector ops configure | 11 ++ tests/tcg/riscv64/semicall.h | 12 +- tests/tcg/multiarch/system/memory.c | 113 ++++++++---------- tests/tcg/riscv64/system.c | 30 +++++ tests/tcg/Makefile.target | 10 +- tests/tcg/aarch64/Makefile.softmmu-target | 3 +- tests/tcg/riscv64/Makefile.softmmu-target | 134 +++++++++++++--------- tests/tcg/riscv64/boot.S | 23 ++++ tests/tcg/riscv64/semihost.ld | 47 ++++++-- 9 files changed, 251 insertions(+), 132 deletions(-) create mode 100644 tests/tcg/riscv64/system.c create mode 100644 tests/tcg/riscv64/boot.S -- 2.47.3