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([180.150.112.50]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39670599275sm2210473a91.0.2026.08.26.22.10.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 22:10:50 -0700 (PDT) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini Cc: Peter Maydell , Weiwei Li , Liu Zhiwei , Chao Liu , Nicholas Piggin , Anirudh Srinivasan , Michael Ellerman , Portia Stephens , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [PATCH 06/12] tests/tcg/riscv64: Enable multiarch system tests Date: Thu, 27 Aug 2026 14:39:45 +0930 Message-ID: <20260827050953.67184-7-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260827050953.67184-1-joel@jms.id.au> References: <20260827050953.67184-1-joel@jms.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=joel.stan@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the boot code and semihosting helpers needed to run the multiarch system tests on riscv64, and add riscv64 to MULTIARCH_SOFTMMU_TARGETS. The aarch64 makefile was used as a guide for the make rules. boot.S does not clear bss as the libmem plugin test would count the stores and fail with a mismatch. Instead the BSS is described as PT_LOAD, so the QEMU ELF loader fills the region with zero, the same as aarch64 and loongarch64. Signed-off-by: Joel Stanley --- tests/tcg/riscv64/system.c | 30 +++++++++++++++++ tests/tcg/Makefile.target | 2 +- tests/tcg/riscv64/Makefile.softmmu-target | 40 ++++++++++++----------- tests/tcg/riscv64/boot.S | 23 +++++++++++++ 4 files changed, 75 insertions(+), 20 deletions(-) create mode 100644 tests/tcg/riscv64/system.c create mode 100644 tests/tcg/riscv64/boot.S diff --git a/tests/tcg/riscv64/system.c b/tests/tcg/riscv64/system.c new file mode 100644 index 000000000000..08196a540f96 --- /dev/null +++ b/tests/tcg/riscv64/system.c @@ -0,0 +1,30 @@ +/* + * RISC-V semihosting support for multiarch test suite + * + * Copyright 2026 Tenstorrent USA Inc + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "semicall.h" + +#define SYS_WRITEC 0x3 +#define SYS_EXIT 0x18 + +#define ADP_Stopped_ApplicationExit 0x20026 + +void __sys_outc(char c) +{ + __semi_call(SYS_WRITEC, (uintptr_t)&c); +} + +void _exit(int code) +{ + const uintptr_t args[2] = { ADP_Stopped_ApplicationExit, (uintptr_t)code }; + + __semi_call(SYS_EXIT, (uintptr_t)args); + + /* Hang if QEMU fails to exit */ + while (1) { + asm volatile("wfi"); + } +} diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index 1b83824ff4e7..d4dd0fec650d 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -129,7 +129,7 @@ else EXTRA_CFLAGS += -ffreestanding -fno-stack-protector # We skip the multiarch tests if the target hasn't provided a boot.S -MULTIARCH_SOFTMMU_TARGETS = i386 alpha aarch64 arm loongarch64 s390x x86_64 +MULTIARCH_SOFTMMU_TARGETS = i386 alpha aarch64 arm loongarch64 s390x x86_64 riscv64 ifneq ($(filter $(TARGET_NAME),$(MULTIARCH_SOFTMMU_TARGETS)),) -include $(SRC_PATH)/tests/tcg/minilib/Makefile.target diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target index f2850a194084..82e8fe2664b0 100644 --- a/tests/tcg/riscv64/Makefile.softmmu-target +++ b/tests/tcg/riscv64/Makefile.softmmu-target @@ -5,9 +5,11 @@ TEST_SRC = $(SRC_PATH)/tests/tcg/riscv64 VPATH += $(TEST_SRC) +CRT_OBJS = boot.o system.o + LINK_SCRIPT = $(TEST_SRC)/semihost.ld -LDFLAGS = -T $(LINK_SCRIPT) -CFLAGS += -g -Og +LDFLAGS = -Wl,-T$(LINK_SCRIPT) -static -nostdlib $(MINILIB_OBJS) -lgcc +CFLAGS += -g -Og $(MINILIB_INC) # Used by riscv64 tcg tests and shared 'multiarch' tests QEMU_CPU = rv64 @@ -53,23 +55,23 @@ test-zicclsm-off.o: test-zicclsm.S $(call quiet-command, \ $(CC) $(CFLAGS) $< -Wa$(COMMA)--noexecstack -c -o $@, CC, $@) -EXTRA_RUNS += run-plugin-doubletrap -run-plugin-doubletrap: doubletrap - $(call run-test, $<, \ - $(QEMU) -monitor none -display none \ - -chardev file$(COMMA)path=$<.out$(COMMA)id=output \ - -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \ - $(QEMU_OPTS) $<) - -EXTRA_RUNS += run-plugin-interruptedmemory -run-plugin-interruptedmemory: interruptedmemory - $(call run-test, $<, \ - $(QEMU) -monitor none -display none \ - -chardev file$(COMMA)path=$<.out$(COMMA)id=output \ - -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \ - $(QEMU_OPTS) $<) +ifeq ($(CONFIG_PLUGIN),y) +EXTRA_RUNS_WITH_PLUGIN += run-plugin-doubletrap-with-libdiscons.so \ + run-plugin-interruptedmemory-with-libdiscons.so +endif CLEANFILES += interruptedmemory doubletrap -# We don't currently support the multiarch system tests -undefine MULTIARCH_TESTS +# Multiarch tests +TESTS += $(MULTIARCH_TESTS) +EXTRA_RUNS += $(MULTIARCH_RUNS) + +.PRECIOUS: $(CRT_OBJS) + +# Build and link the multiarch tests +%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) + $(call quiet-command, \ + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(CRT_OBJS), CC, $@) + +# Default is zicclsm=true, so misaligned accesses must work +memory: private CFLAGS += -DCHECK_UNALIGNED=1 diff --git a/tests/tcg/riscv64/boot.S b/tests/tcg/riscv64/boot.S new file mode 100644 index 000000000000..b403549345a1 --- /dev/null +++ b/tests/tcg/riscv64/boot.S @@ -0,0 +1,23 @@ +/* + * RISC-V boot code for multiarch test suite + * + * Copyright 2026 Tenstorrent USA Inc + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#define MSTATUS_VS 0x00000600 +#define MSTATUS_FS 0x00006000 + +.section .text._start + .global _start + .type _start, @function +_start: + /* Enable FPU and vector unit */ + li t0, (MSTATUS_FS | MSTATUS_VS) + csrs mstatus, t0 + la sp, __stack_top + call main + +exit: + /* exit with main()'s return code */ + call _exit -- 2.47.3