From: sashiko-bot@kernel.org
To: "Linmao Li" <lilinmao@kylinos.cn>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI: tegra264: Fix Link Capabilities register offset
Date: Thu, 27 Aug 2026 09:46:48 +0000 [thread overview]
Message-ID: <20260827094648.678761F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260827093919.2825467-1-lilinmao@kylinos.cn>
> The PCI Express Link Capabilities and Link Status registers are at offsets
> 0x0c and 0x12 from the capability header, respectively. Since the driver
> uses 0x5a for Link Status, Link Capabilities starts at 0x54, not 0x56.
>
> Reading a 16-bit value at 0x56 returns the upper half of the Link
> Capabilities register. When a hotplug-capable port has no link during
> probe, tegra264_pcie_icc_set() consequently derives the maximum speed and
> width from unrelated bits and requests the wrong interconnect bandwidth.
>
> Use the correct Link Capabilities offset.
>
> Fixes: 01c3c27a0ef6 ("PCI: tegra264: Add Tegra264 support")
> Signed-off-by: Linmao Li <lilinmao@kylinos.cn>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260827093919.2825467-1-lilinmao@kylinos.cn?part=1
next prev parent reply other threads:[~2026-08-27 9:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 9:39 [PATCH] PCI: tegra264: Fix Link Capabilities register offset Linmao Li
2026-08-27 9:46 ` sashiko-bot [this message]
2026-08-27 10:02 ` Thierry Reding
2026-08-27 17:03 ` Bjorn Helgaas
2026-08-27 17:11 ` Thierry Reding
2026-09-02 14:24 ` Manivannan Sadhasivam
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