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envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Tanushree Shah Moving the following instructions to decodetree specification: lmw : D-form stmw : D-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the "-d in_asm,op" flag. Additionally, validated using small assembly tests confirming the the correct register store/load behavior. Also, confirmed the register values are same before and after the change. Signed-off-by: Tanushree Shah Reviewed-by: Glenn Miles Reviewed-by: Amit Machhiwal Signed-off-by: Chinmay Rath --- target/ppc/helper.h | 4 +-- target/ppc/insn32.decode | 3 ++ target/ppc/mem_helper.c | 4 +-- target/ppc/translate.c | 39 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 32 ++++++++++++++++++ 5 files changed, 39 insertions(+), 43 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 7da752c69b..ec3350fee8 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -43,8 +43,8 @@ DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) #endif -DEF_HELPER_3(lmw, void, env, tl, i32) -DEF_HELPER_FLAGS_3(stmw, TCG_CALL_NO_WG, void, env, tl, i32) +DEF_HELPER_3(LMW, void, env, tl, i32) +DEF_HELPER_FLAGS_3(STMW, TCG_CALL_NO_WG, void, env, tl, i32) DEF_HELPER_4(LSW, void, env, tl, i32, i32) DEF_HELPER_5(LSWX, void, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_4(STSW, TCG_CALL_NO_WG, void, env, tl, i32, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 92ee278f63..ef128f63c1 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -354,6 +354,7 @@ LVDX 011111 ..... ..... ..... 0000010001 - @X LSKU 111010 ..... ..... ............. 0 11 @DD LCXU 111010 ..... ..... ............. 1 11 @DD +LMW 101110 ..... ..... ................ @D ### Fixed-Point Atomic Load/Store Instructions @@ -399,6 +400,8 @@ STBCIX 011111 ..... ..... ..... 1111010101 - @X STHBRX 011111 ..... ..... ..... 1110010110 - @X STWBRX 011111 ..... ..... ..... 1010010110 - @X +STMW 101111 ..... ..... ................ @D + ### Fixed-Point Compare Instructions CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 10c648cf06..dc5eab8c76 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -73,7 +73,7 @@ static void *probe_contiguous(CPUPPCState *env, target_ulong addr, uint32_t nb, return NULL; } -void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) +void helper_LMW(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr = GETPC(); int mmu_idx = ppc_env_mmu_index(env, false); @@ -98,7 +98,7 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) } } -void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) +void helper_STMW(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr = GETPC(); int mmu_idx = ppc_env_mmu_index(env, false); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ce94f9e4e6..880915f3da 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2455,43 +2455,6 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); #endif /* TARGET_PPC64 */ -/*** Integer load and store multiple ***/ - -/* lmw */ -static void gen_lmw(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 = tcg_temp_new(); - t1 = tcg_constant_i32(rD(ctx->opcode)); - gen_addr_imm_index(ctx, t0, 0); - gen_helper_lmw(tcg_env, t0, t1); -} - -/* stmw */ -static void gen_stmw(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 = tcg_temp_new(); - t1 = tcg_constant_i32(rS(ctx->opcode)); - gen_addr_imm_index(ctx, t0, 0); - gen_helper_stmw(tcg_env, t0, t1); -} - - #if !defined(CONFIG_USER_ONLY) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { @@ -4695,8 +4658,6 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), /* handles stfdp, stxsd, stxssp */ GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), -GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index efef56a119..8475205f14 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -288,6 +288,38 @@ static bool trans_STQCX(DisasContext *ctx, arg_STQCX *a) return true; } +/* Load/Store Multiple Word */ +static bool do_ldst_multiple(DisasContext *ctx, arg_D *a, bool store) +{ + TCGv ea; + TCGv_i32 reg; + + REQUIRE_INSNS_FLAGS(ctx, INTEGER); + + /* Little-endian mode is not supported for multiple word operations */ + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + + gen_set_access_type(ctx, ACCESS_INT); + + reg = tcg_constant_i32(a->rt); + ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->si)); + + /* Call the appropriate helper function */ + if (store) { + gen_helper_STMW(tcg_env, ea, reg); + } else { + gen_helper_LMW(tcg_env, ea, reg); + } + + return true; +} + +TRANS(LMW, do_ldst_multiple, false) +TRANS(STMW, do_ldst_multiple, true) + /* * Fixed-Point Compare Instructions */ -- 2.55.0