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envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org PPC2_ISA207S is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_ISA207S could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Amit Machhiwal Reviewed-by: Glenn Miles Reviewed-by: Richard Henderson Signed-off-by: Chinmay Rath --- hw/ppc/spapr_caps.c | 2 +- linux-user/ppc/elfload.c | 2 +- target/ppc/cpu.h | 5 +---- target/ppc/cpu_init.c | 3 +-- target/ppc/cpu_init.h | 2 +- target/ppc/tcg-excp_helper.c | 8 ++++---- target/ppc/translate.c | 6 +++--- target/ppc/translate/bhrb-impl.c.inc | 4 ++-- target/ppc/translate/branch-impl.c.inc | 2 +- target/ppc/translate/processor-ctrl-impl.c.inc | 8 ++++---- 10 files changed, 19 insertions(+), 23 deletions(-) diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index f4a26a85b5..0d659e9b02 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -676,7 +676,7 @@ static void cap_ail_mode_3_apply(SpaprMachineState *spapr, if (tcg_enabled()) { /* AIL-3 is only supported on POWER8 and above CPUs. */ - if (!(pcc->insns_flags2 & PPC2_ISA207S)) { + if (!(pcc->insns_flags2 & PPC2_ISA207)) { error_setg(errp, "TCG only supports cap-ail-mode-3 on POWER8 and later CPUs"); error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n"); return; diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c index 8c40f1a663..7bf49e7c0b 100644 --- a/linux-user/ppc/elfload.c +++ b/linux-user/ppc/elfload.c @@ -116,7 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0) GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); - GET_FEATURE2((PPC2_ISA207 | PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 | + GET_FEATURE2(PPC2_ISA207, (QEMU_PPC_FEATURE2_ARCH_2_07 | QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR)); GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 00676cea2b..4a77607f80 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2577,8 +2577,6 @@ enum { PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL, /* ISA 2.06B floating point test instructions */ PPC2_FP_TST_ISA206 = 0x0000000000000800ULL, - /* PowerISA 2.07 Book3s specification */ - PPC2_ISA207S = 0x0000000000008000ULL, /* Double precision floating point conversion for signed integer 64 */ PPC2_FP_CVT_S64 = 0x0000000000010000ULL, /* Transactional Memory (ISA 2.07, Book II) */ @@ -2603,8 +2601,7 @@ enum { #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ - PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_ISA207S | PPC2_DFP | \ + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_DFP | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ PPC2_BCDA_ISA206 | PPC2_PPE42 | PPC2_PPE42X | \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c251426b2e..6c626843c9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6349,8 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data) pcc->insns_flags2 = PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_FP_TST_ISA206 | PPC2_ISA205 | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; pcc->msr_mask = (1ull << MSR_SF) | diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 73f014c82a..4ba559d8af 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -18,7 +18,7 @@ (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_ISA205 | \ - PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ + PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206) #define PPC_INSNS_FLAGS2_POWER9 \ diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index d06d3f8642..93aedb0c8e 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -314,7 +314,7 @@ void ppc_cpu_debug_excp_handler(CPUState *cs) #if defined(TARGET_PPC64) CPUPPCState *env = cpu_env(cs); - if (env->insns_flags2 & PPC2_ISA207S) { + if (env->insns_flags2 & PPC2_ISA207) { if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { env->spr[SPR_DAR] = cs->watchpoint_hit->hitaddr; @@ -336,7 +336,7 @@ bool ppc_cpu_debug_check_breakpoint(CPUState *cs) #if defined(TARGET_PPC64) CPUPPCState *env = cpu_env(cs); - if (env->insns_flags2 & PPC2_ISA207S) { + if (env->insns_flags2 & PPC2_ISA207) { target_ulong priv; priv = env->spr[SPR_CIABR] & PPC_BITMASK(62, 63); @@ -365,7 +365,7 @@ bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) bool wt, wti, hv, sv, pr; uint32_t dawrx; - if ((env->insns_flags2 & PPC2_ISA207S) && + if ((env->insns_flags2 & PPC2_ISA207) && (wp == env->dawr_watchpoint[0])) { dawrx = env->spr[SPR_DAWRX0]; } else if ((env->insns_flags2 & PPC2_ISA310) && @@ -849,7 +849,7 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) void helper_book3s_trace(CPUPPCState *env, target_ulong prev_ip) { uint32_t error_code = 0; - if (env->insns_flags2 & PPC2_ISA207S) { + if (env->insns_flags2 & PPC2_ISA207) { /* Load/store reporting, SRR1[35, 36] and SDAR, are not implemented. */ env->spr[SPR_POWER_SIAR] = prev_ip; error_code = PPC_BIT(33); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f46e2167ea..6408ed7de7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2775,7 +2775,7 @@ static inline void gen_op_mfspr(DisasContext *ctx) } } else { /* ISA 2.07 defines these as no-ops */ - if ((ctx->insns_flags2 & PPC2_ISA207S) && + if ((ctx->insns_flags2 & PPC2_ISA207) && (sprn >= 808 && sprn <= 811)) { /* This is a nop */ return; @@ -2841,7 +2841,7 @@ static void gen_mtspr(DisasContext *ctx) } } else { /* ISA 2.07 defines these as no-ops */ - if ((ctx->insns_flags2 & PPC2_ISA207S) && + if ((ctx->insns_flags2 & PPC2_ISA207) && (sprn >= 808 && sprn <= 811)) { /* This is a nop */ return; @@ -4135,7 +4135,7 @@ TRANS64(LDARX, do_load_locked, DEF_MEMOP(MO_UQ)) static bool trans_LQARX(DisasContext *ctx, arg_LQARX *a) { REQUIRE_64BIT(ctx); - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); #if defined(TARGET_PPC64) TCGv EA; TCGv_i128 t16; diff --git a/target/ppc/translate/bhrb-impl.c.inc b/target/ppc/translate/bhrb-impl.c.inc index 3a19bc4555..4b3914a1f6 100644 --- a/target/ppc/translate/bhrb-impl.c.inc +++ b/target/ppc/translate/bhrb-impl.c.inc @@ -14,7 +14,7 @@ static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg) { - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); TCGv_i32 bhrbe = tcg_constant_i32(arg->bhrbe); gen_helper_mfbhrbe(cpu_gpr[arg->rt], tcg_env, bhrbe); return true; @@ -22,7 +22,7 @@ static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg) static bool trans_CLRBHRB(DisasContext *ctx, arg_CLRBHRB *arg) { - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); gen_helper_clrbhrb(tcg_env); return true; } diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/branch-impl.c.inc index e5b64ca84e..51fcabff63 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -14,7 +14,7 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) { - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); translator_io_start(&ctx->base); gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/translate/processor-ctrl-impl.c.inc index cfcca28267..cb125cfa72 100644 --- a/target/ppc/translate/processor-ctrl-impl.c.inc +++ b/target/ppc/translate/processor-ctrl-impl.c.inc @@ -23,7 +23,7 @@ static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a) { - if (!(ctx->insns_flags2 & PPC2_ISA207S)) { + if (!(ctx->insns_flags2 & PPC2_ISA207)) { /* * Before Power ISA 2.07, processor control instructions were only * implemented in the "Embedded.Processor Control" category. @@ -47,7 +47,7 @@ static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a) static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a) { - if (!(ctx->insns_flags2 & PPC2_ISA207S)) { + if (!(ctx->insns_flags2 & PPC2_ISA207)) { /* * Before Power ISA 2.07, processor control instructions were only * implemented in the "Embedded.Processor Control" category. @@ -72,7 +72,7 @@ static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a) static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a) { REQUIRE_64BIT(ctx); - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_SV(ctx); #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]); @@ -85,7 +85,7 @@ static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a) static bool trans_MSGSNDP(DisasContext *ctx, arg_X_rb *a) { REQUIRE_64BIT(ctx); - REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + REQUIRE_INSNS_FLAGS2(ctx, ISA207); REQUIRE_SV(ctx); #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]); -- 2.55.0