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envelope-from=amachhiw@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2026/08/27 06:59 PM, Chinmay Rath wrote: > From: Vishal Chourasia > > Moving the following instructions to decodetree specification: > brd, brw, brh : X-form > > The changes were verified by validating that the tcg ops generated by > those instructions remain the same, which were captured with the > `-d in_asm,op` flag. > > This also includes improvements from review feedback: > - Add TARGET_PPC64 guards with qemu_build_not_reached() for 32-bit builds > > Signed-off-by: Vishal Chourasia > Reviewed-by: Glenn Miles > Signed-off-by: Chinmay Rath > --- > target/ppc/insn32.decode | 5 +++ > target/ppc/translate.c | 35 ---------------- > target/ppc/translate/fixedpoint-impl.c.inc | 48 ++++++++++++++++++++++ > 3 files changed, 53 insertions(+), 35 deletions(-) Thanks for incorporating the review comments. Reviewed-by: Amit Machhiwal > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index 1e263449a5..7bbe1f8838 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -320,6 +320,11 @@ MFMSR 011111 ..... ----- ----- 0001010011 - @X_t > MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l > MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l > > +### Fixed-Point Byte-Reverse Instructions > +BRW 011111 ..... ..... ----- 0010011011 - @X_sa > +BRD 011111 ..... ..... ----- 0010111011 - @X_sa > +BRH 011111 ..... ..... ----- 0011011011 - @X_sa > + > ### Fixed-Point Load Instructions > > LBZ 100010 ..... ..... ................ @D > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 1d069c5250..20d3e7c1ab 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -4519,42 +4519,7 @@ static void gen_dform3D(DisasContext *ctx) > return gen_invalid(ctx); > } > > -#if defined(TARGET_PPC64) > -/* brd */ > -static void gen_brd(DisasContext *ctx) > -{ > - tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); > -} > - > -/* brw */ > -static void gen_brw(DisasContext *ctx) > -{ > - tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); > - tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); > - > -} > - > -/* brh */ > -static void gen_brh(DisasContext *ctx) > -{ > - TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); > - TCGv_i64 t1 = tcg_temp_new_i64(); > - TCGv_i64 t2 = tcg_temp_new_i64(); > - > - tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); > - tcg_gen_and_i64(t2, t1, mask); > - tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); > - tcg_gen_shli_i64(t1, t1, 8); > - tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); > -} > -#endif > - > static opcode_t opcodes[] = { > -#if defined(TARGET_PPC64) > -GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), > -GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), > -GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), > -#endif > GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), > GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), > GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), > diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc > index 8475205f14..0e1960a272 100644 > --- a/target/ppc/translate/fixedpoint-impl.c.inc > +++ b/target/ppc/translate/fixedpoint-impl.c.inc > @@ -17,6 +17,54 @@ > * License along with this library; if not, see . > */ > > +/* > + * Byte-Reverse Instructions > + */ > +static bool trans_BRD(DisasContext *ctx, arg_BRD *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_INSNS_FLAGS2(ctx, ISA310); > +#if defined(TARGET_PPC64) > + tcg_gen_bswap64_i64(cpu_gpr[a->ra], cpu_gpr[a->rs]); > +#else > + qemu_build_not_reached(); > +#endif > + return true; > +} > + > +static bool trans_BRW(DisasContext *ctx, arg_BRW *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_INSNS_FLAGS2(ctx, ISA310); > +#if defined(TARGET_PPC64) > + tcg_gen_bswap64_i64(cpu_gpr[a->ra], cpu_gpr[a->rs]); > + tcg_gen_rotli_i64(cpu_gpr[a->ra], cpu_gpr[a->ra], 32); > +#else > + qemu_build_not_reached(); > +#endif > + return true; > +} > + > +static bool trans_BRH(DisasContext *ctx, arg_BRH *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_INSNS_FLAGS2(ctx, ISA310); > +#if defined(TARGET_PPC64) > + TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); > + TCGv_i64 t1 = tcg_temp_new_i64(); > + TCGv_i64 t2 = tcg_temp_new_i64(); > + > + tcg_gen_shri_i64(t1, cpu_gpr[a->rs], 8); > + tcg_gen_and_i64(t2, t1, mask); > + tcg_gen_and_i64(t1, cpu_gpr[a->rs], mask); > + tcg_gen_shli_i64(t1, t1, 8); > + tcg_gen_or_i64(cpu_gpr[a->ra], t1, t2); > +#else > + qemu_build_not_reached(); > +#endif > + return true; > +} > + > /* > * Fixed-Point Load/Store Instructions > */ > -- > 2.55.0 >