From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A478B3D9DBA; Thu, 27 Aug 2026 22:48:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787870892; cv=none; b=cAUT9emGQXpRP36wyRo69gWFIWID6yl9YJOPjqJPcyeNNYOeeQwaKc/M6En0kDo9g/WBEDDvgb4NTCenbQep0riOjNtgWBvzu/XHK1pWfwLjJkmkbJpqmXjein7/7s4qiVwNrlVpW+OsmpGjKbmXojp4sCAzmxqK/jRPW+R8wgI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787870892; c=relaxed/simple; bh=PpmY5w7h10sz9H8v4LgnkHC8Duc5WPj45VSrHR3cKKI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BlPEtSZ85ZasBrnAbzG7KiqtFbroMi5zyVL8VkKtad94dzcX7AIOSUvDKJcPGIAX+YE1RFPKMi149iMd1alb5KIFrClRUxcfg96kNytEadNZChr1hRK4LpeNNlGaOrlunrC9XHo6q0hOtN3aY310PMYndkLLYmEoiSTwjjh8j/I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EdBBg+PD; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EdBBg+PD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787870890; x=1819406890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PpmY5w7h10sz9H8v4LgnkHC8Duc5WPj45VSrHR3cKKI=; b=EdBBg+PDe8AWa1tiD785DdBcV5bttixo+5PtNJlh1Cl7rBuTSugwCPkz EpH6hN4MOrc5uDacJwo3qY2PdRfxTKGVedGmv14l1vKqs8YVysnNqgz3t 3t/0pwaRED4ThH1dJVsbZ2RMUkIPSFsJawpmzVLaCOMWUzLpFDxBLwSr4 Ozr+AjTxIbojQ/7v+BaDFWPp7MNchKv5GufyN+mOLV9A4AqTanXRjGz7k Pc7laa5S1ntV/lXdIBrbcwQhytZVt0WfQYP+bC12Yp9go44kubkm6u8TG qUaFjs7G2mAJoIABDOUfHDv5pYdTyttwoorz3sCAxnW0NIibaTlaqZo6l g==; X-CSE-ConnectionGUID: dyzKhSIFSp+B8Pu6+RynCQ== X-CSE-MsgGUID: 9qiNyt2MT324W/VP8WEjOQ== X-IronPort-AV: E=McAfee;i="6800,10657,11888"; a="113914859" X-IronPort-AV: E=Sophos;i="6.25,247,1779174000"; d="scan'208";a="113914859" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2026 15:48:07 -0700 X-CSE-ConnectionGUID: IHlqoiajQPC7HZ4y1lvDAA== X-CSE-MsgGUID: IHRYPhroTPKy4OZXzIy4Ww== X-ExtLoop1: 1 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2026 15:48:07 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Andi Kleen , Jim Mattson , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Subject: [PATCH v2 07/16] KVM: x86/pmu: Expose kvm_host_pmu to vendor modules Date: Thu, 27 Aug 2026 15:37:46 -0700 Message-ID: <20260827223755.143247-8-zide.chen@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260827223755.143247-1-zide.chen@intel.com> References: <20260827223755.143247-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit kvm_host_pmu holds the unadulterated host PMU capabilities, which can be used to compare against guest capabilities to determine whether certain MSRs should be intercepted by KVM. Exposing it directly avoids the need to introduce per-field accessors, which would add boilerplate without hiding any implementation detail worth encapsulating. Opportunistically, fix typo "Unadultered" in the comment. Signed-off-by: Zide Chen --- arch/x86/kvm/pmu.c | 5 +++-- arch/x86/kvm/pmu.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index b0fcd0a538d2..7837e2e1af98 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -27,8 +27,9 @@ /* This is enough to filter the vast majority of currently defined events. */ #define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300 -/* Unadultered PMU capabilities of the host, i.e. of hardware. */ -static struct x86_pmu_capability __read_mostly kvm_host_pmu; +/* Unadulterated PMU capabilities of the host, i.e. of hardware. */ +struct x86_pmu_capability __read_mostly kvm_host_pmu; +EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_host_pmu); /* KVM's PMU capabilities, i.e. the intersection of KVM and hardware support. */ struct x86_pmu_capability __read_mostly kvm_pmu_cap; diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index b7a319b1eccc..9a658ae5b268 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -252,6 +252,7 @@ static inline bool pmc_is_locally_enabled(struct kvm_pmc *pmc) return !kvm_pmu_call(pmc_is_disabled_in_current_mode)(pmc); } +extern struct x86_pmu_capability kvm_host_pmu; extern struct x86_pmu_capability kvm_pmu_cap; void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_ops); -- 2.55.0