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Davis" , Vignesh Raghavendra , Bryan Brattlof , Vaishnav Achath , Jayesh Choudhary , Simon Glass , Alper Nebi Yasak Cc: Markus Schneider-Pargmann , Kendall Willis , Udit Kumar , Abhash Kumar , Thomas Richard , Gregory CLEMENT , Thomas Petazzoni , Richard Genoud , u-boot@lists.u-boot-project.org Subject: [PATCH v5 15/21] arm: mach-k3: j721e: Enable LPM resume flow for J7200/J721e SOC Date: Fri, 28 Aug 2026 15:57:24 +0200 Message-ID: <20260828135730.1565643-16-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260828135730.1565643-1-richard.genoud@bootlin.com> References: <20260828135730.1565643-1-richard.genoud@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org From: "Thomas Richard (TI)" Add support for resuming from suspend in board_init_f. The resume state of the SOC is identified and lpm resume sequence is followed accordingly. First, add the board specific part of the exit retention sequence for k3-ddrss following the DDR resume sequence: - exit DDR from retention - de-assert the DDR_RET pin - restore DDR max frequency - exit DDR from low power Then: - Extract context address from devicetree and send to TIFS. - Power on the rproc cluster. - Replay the certificates attached to saved images of ATF and OPTEE. - Resume sequence for context restore and rproc resume. - Image entry to DM firmware. (All those steps are done in do_resume()) The context address area is firewalled by TIFS to protect it from other hosts. Co-developed-by: Gregory CLEMENT (TI) Signed-off-by: Gregory CLEMENT (TI) Signed-off-by: Thomas Richard (TI) Co-developed-by: Prasanth Babu Mantena Signed-off-by: Prasanth Babu Mantena Co-developed-by: Richard Genoud (TI) Signed-off-by: Richard Genoud (TI) --- arch/arm/mach-k3/j721e/j721e_init.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index f9af0288cf66..fce6702be687 100644 --- a/arch/arm/mach-k3/j721e/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -20,9 +20,12 @@ #include #include #include +#include +#include #include "../sysfw-loader.h" #include "../common.h" +#include "../lpm-common.h" /* NAVSS North Bridge (NB) registers */ #define NAVSS0_NBSS_NB0_CFG_MMRS 0x03802000 @@ -46,6 +49,10 @@ #define DEV_A72SS0_CORE0_ID 4 #define DEV_A72SS0_CORE0_MSMC_CLK_ID 1 +/* DDR retention bits */ +#define DDR_RET_VAL BIT(1) +#define DDR_RET_CLK BIT(2) + #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { #if defined(CONFIG_SOC_K3_J721E) @@ -298,6 +305,7 @@ void board_init_f(ulong dummy) { int ret; #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW) + struct k3_ddrss_regs regs; struct udevice *dev; #endif /* @@ -410,6 +418,22 @@ void board_init_f(ulong dummy) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) panic("DRAM init failed: %d\n", ret); + + if (j7xx_board_is_resuming()) { + /* + * The DDR resume sequence is: + * - exit DDR from retention + * - de-assert the DDR_RET pin + * - restore DDR max frequency + * - exit DDR from low power + */ + k3_ddrss_lpddr4_exit_retention(dev, ®s); + k3_deassert_ddr_ret("pmic@4c", DDR_RET_VAL, DDR_RET_CLK, true); + k3_ddrss_lpddr4_change_freq(dev); + k3_ddrss_lpddr4_exit_low_power(dev, ®s); + + do_resume(); + } #endif spl_enable_cache();