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Davis" , Vignesh Raghavendra , Bryan Brattlof , Vaishnav Achath , Jayesh Choudhary , Simon Glass , Alper Nebi Yasak Cc: Markus Schneider-Pargmann , Kendall Willis , Udit Kumar , Abhash Kumar , Thomas Richard , Gregory CLEMENT , Thomas Petazzoni , Richard Genoud , u-boot@lists.u-boot-project.org Subject: [PATCH v5 18/21] arm: mach-k3: j721s2: Enable LPM resume flow Date: Fri, 28 Aug 2026 15:57:27 +0200 Message-ID: <20260828135730.1565643-19-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260828135730.1565643-1-richard.genoud@bootlin.com> References: <20260828135730.1565643-1-richard.genoud@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org From: "Thomas Richard (TI)" Add the board specific part of the exit retention sequence for k3-ddrss: - exit DDR from retention - de-assert the DDR_RET pin - restore DDR max frequency - exit DDR from low power Then generic resume path is run. Signed-off-by: Thomas Richard (TI) --- arch/arm/mach-k3/j721s2/j721s2_init.c | 49 ++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index 780d853423f8..e35b00ff2dbb 100644 --- a/arch/arm/mach-k3/j721s2/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -16,12 +16,20 @@ #include #include #include +#include #include +#include #include #include "../sysfw-loader.h" +#include "../lpm-common.h" #include "../common.h" +#define MAX_DDR_CONTROLLERS 2 + +/* DDR retention bits */ +#define DDR_RET_VAL BIT(3) + /* NAVSS North Bridge (NB) */ #define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000 #define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000 @@ -262,9 +270,12 @@ bool check_rom_loaded_sysfw(void) void k3_mem_init(void) { struct udevice *dev; - int ret; + int ret, ctrl = 0; if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) { + struct udevice *devs[MAX_DDR_CONTROLLERS]; + struct k3_ddrss_regs regs[MAX_DDR_CONTROLLERS]; + ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev); if (ret) panic("Probe of msmc failed: %d\n", ret); @@ -272,10 +283,40 @@ void k3_mem_init(void) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) panic("DRAM 0 init failed: %d\n", ret); + devs[0] = dev; + ctrl++; - ret = uclass_next_device_err(&dev); - if (ret && ret != -ENODEV) - panic("DRAM 1 init failed: %d\n", ret); + while (ctrl < MAX_DDR_CONTROLLERS) { + ret = uclass_next_device_err(&dev); + if (ret == -ENODEV) + break; + + if (ret) + panic("DRAM %d init failed: %d\n", ctrl, ret); + devs[ctrl] = dev; + ctrl++; + } + + if (j7xx_board_is_resuming()) { + /* exit DDRs from retention */ + for (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++) + k3_ddrss_lpddr4_exit_retention(devs[ctrl], + ®s[ctrl]); + + /* de-assert DDR_RET pin */ + k3_deassert_ddr_ret("pmic@4c", DDR_RET_VAL, 0, false); + + /* restore DDR max frequency */ + for (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++) + k3_ddrss_lpddr4_change_freq(devs[ctrl]); + + /* exit DDR from low power */ + for (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++) + k3_ddrss_lpddr4_exit_low_power(devs[ctrl], + ®s[ctrl]); + + do_resume(); + } } spl_enable_cache(); }