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Davis" , Vignesh Raghavendra , Bryan Brattlof , Vaishnav Achath , Jayesh Choudhary , Simon Glass , Alper Nebi Yasak Cc: Markus Schneider-Pargmann , Kendall Willis , Udit Kumar , Abhash Kumar , Thomas Richard , Gregory CLEMENT , Thomas Petazzoni , Richard Genoud , u-boot@lists.u-boot-project.org Subject: [PATCH v5 08/21] board: mach-k3: r5: common: enable GTC after core_resume Date: Fri, 28 Aug 2026 15:57:17 +0200 Message-ID: <20260828135730.1565643-9-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260828135730.1565643-1-richard.genoud@bootlin.com> References: <20260828135730.1565643-1-richard.genoud@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org From: Abhash Kumar Jha The GTC counter values are restored in the resume sequence by TIFS as part of the core_resume API. Enable GTC counter after it is restored. Also add a check to make sure that rproc_load only enables the GTC counter in the case of a cold boot. Signed-off-by: Abhash Kumar Jha Co-developed-by: Richard Genoud (TI) Signed-off-by: Richard Genoud (TI) --- arch/arm/mach-k3/r5/lpm-common.c | 11 +++++++++++ drivers/remoteproc/ti_k3_arm64_rproc.c | 10 ++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/r5/lpm-common.c b/arch/arm/mach-k3/r5/lpm-common.c index ab39ea0cd67d..4f515b51fd40 100644 --- a/arch/arm/mach-k3/r5/lpm-common.c +++ b/arch/arm/mach-k3/r5/lpm-common.c @@ -311,6 +311,7 @@ static void resume_rproc_f(void) { struct power_domain rproc_pwrdmn; struct udevice *dev; + void *gtc_base; int ret; ret = uclass_get_device_by_seq(UCLASS_REMOTEPROC, 1, &dev); @@ -321,6 +322,16 @@ static void resume_rproc_f(void) if (ret) panic("power_domain_get_rproc() failed: %d\n", ret); + gtc_base = dev_read_addr_ptr(dev); + if (!gtc_base) + panic("Get GTC address failed\n"); + +#define GTC_CNTCR_REG 0x0 +#define GTC_CNTR_EN 0x3 + + /* GTC counter values have been restored by TIFS, so enable the counter */ + writel(GTC_CNTR_EN, gtc_base + GTC_CNTCR_REG); + ret = power_domain_on(&rproc_pwrdmn); if (ret) panic("power_domain_on failed: %d\n", ret); diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c index 403c6bed2e8c..9b8a6b7dc53a 100644 --- a/drivers/remoteproc/ti_k3_arm64_rproc.c +++ b/drivers/remoteproc/ti_k3_arm64_rproc.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "ti_sci_proc.h" #define INVALID_ID 0xff @@ -78,8 +79,13 @@ static int k3_arm64_load(struct udevice *dev, ulong addr, ulong size) /* Store the clock frequency down for GTC users to pick up */ writel((u32)gtc_rate, rproc->gtc_base + GTC_CNTFID0_REG); - /* Enable the timer before starting remote core */ - writel(GTC_CNTR_EN, rproc->gtc_base + GTC_CNTCR_REG); + if (!j7xx_board_is_resuming()) { + /* + * In case of a fresh boot, enable the timer before + * starting the remote core. + */ + writel(GTC_CNTR_EN, rproc->gtc_base + GTC_CNTCR_REG); + } /* * Setting the right clock frequency would have taken care by