Re: [PATCH 2/2] gpio: tegra186: Add support for Tegra268

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Omitting Port X from `tegra268_main_ports` creates a zero-initialized array hole at index 7 that inadvertently overwrites Port T's interrupt routing configuration with zero, disabling its interrupts.
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commit 8b9bac08700ce95c0c1a37f57510a697c2d7b282
Author: Jon Hunter <jonathanh@nvidia.com>

gpio: tegra186: Add support for Tegra268
    
Add support for the 3 GPIO controllers, main, AON and UPHY, that are
present on the Tegra268 device. Tegra268 has the same 3 GPIO controllers
as Tegra264, but a subset of the GPIOs. Therefore, we can re-use the
Tegra264 device-tree port definitions for Tegra268 and avoid duplicating
these.

> diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
> index d9a2dedf50eae..34e084c95d7a9 100644
> --- a/drivers/gpio/gpio-tegra186.c
> +++ b/drivers/gpio/gpio-tegra186.c
> @@ -1419,6 +1419,71 @@ static const struct tegra_gpio_soc tegra264_uphy_soc = {
>  	.has_vm_support = true,
>  };
>  
> +static const struct tegra_gpio_port tegra268_main_ports[] = {
> +	TEGRA264_MAIN_GPIO_PORT(F, 3, 0, 8),
> +	TEGRA264_MAIN_GPIO_PORT(G, 3, 1, 5),
> +	TEGRA264_MAIN_GPIO_PORT(H, 1, 0, 8),
> +	TEGRA264_MAIN_GPIO_PORT(J, 1, 1, 8),
> +	TEGRA264_MAIN_GPIO_PORT(K, 1, 2, 8),
> +	TEGRA264_MAIN_GPIO_PORT(L, 1, 3, 8),
> +	TEGRA264_MAIN_GPIO_PORT(M, 1, 4, 2),
> +	TEGRA264_MAIN_GPIO_PORT(P, 2, 0, 8),
> +	TEGRA264_MAIN_GPIO_PORT(Q, 2, 1, 8),
> +	TEGRA264_MAIN_GPIO_PORT(R, 2, 2, 8),
> +	TEGRA264_MAIN_GPIO_PORT(S, 2, 3, 2),
> +	TEGRA264_MAIN_GPIO_PORT(T, 0, 0, 7),
> +	TEGRA264_MAIN_GPIO_PORT(U, 0, 1, 8),
> +	TEGRA264_MAIN_GPIO_PORT(V, 0, 2, 8),
> +	TEGRA264_MAIN_GPIO_PORT(W, 0, 3, 8),
> +	TEGRA264_MAIN_GPIO_PORT(Y, 0, 5, 8),
> +	TEGRA264_MAIN_GPIO_PORT(Z, 0, 6, 8),
> +	TEGRA264_MAIN_GPIO_PORT(AL, 0, 4, 3),
> +};

[Severity: High]
Does omitting Port X from tegra268_main_ports[] create a zero-initialized
gap in this sparse array that inadvertently disables Port T's interrupts?

The TEGRA264_MAIN_GPIO_PORT macro uses designated array initializers mapped
to explicit enum indices. By omitting Port X (index 7), the array has a
zero-initialized hole at index 7 with bank=0, port=0, and pins=0.

Later during the driver's probe phase, tegra186_gpio_init_route_mapping()
iterates up to num_ports:

drivers/gpio/gpio-tegra186.c:tegra186_gpio_init_route_mapping() {
    ...
    for (i = 0; i < gpio->soc->num_ports; i++) {
        const struct tegra_gpio_port *port = &gpio->soc->ports[i];
        unsigned int offset, p = port->port;
        ...
        offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0);
        ...
        value = readl(base + offset);
        value = BIT(port->pins) - 1;
        writel(value, base + offset);
    }
}

Because the loop iterates without skipping empty entries, when it reaches
index 7, it maps the coordinates to bank 0, port 0. This overlaps exactly
with Port T which was already configured at index 0.

Could this cause the code to calculate BIT(0) - 1, yielding 0, and write
0 to the INT_ROUTE_MAPPING register, overwriting and destroying the valid
configuration previously set for Port T?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260828-tegra-tegra268-gpio-v1-0-317bd91295e2@nvidia.com?part=2