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Sat, 29 Aug 2026 10:03:29 -0700 (PDT) Received: from [127.0.1.1] ([151.51.168.243]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482fbb32ce2sm12163133f8f.33.2026.08.29.10.03.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Aug 2026 10:03:29 -0700 (PDT) Sender: Massimo Pegorer From: Massimo Pegorer Subject: [PATCH 0/2] Support multiple DDR configs in PX30 TPL Date: Sat, 29 Aug 2026 19:03:10 +0200 Message-Id: <20260829-ddr-multi-v1-0-c0c7837aed20@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAM4Qk2oC/yXM3wpAMBSA8VdZ59qKWVpeRS7YDo4Y7Y+UvLvh8 ldf3wUeHaGHml3g8CBPm00oMgZ66uyInEwyiFxUuRKKG+P4GpdAXGg5mEqWUmoFqd8dDnR+r6b 97WM/ow7vAO77AZgaoxRtAAAA X-Change-ID: 20260828-ddr-multi-2c4fd64344c8 To: Simon Glass , u-boot@lists.u-boot-project.org Cc: Quentin Schulz , Kever Yang , Tom Rini , Massimo Pegorer X-Mailer: b4 0.15.2 X-Mailman-Approved-At: Sat, 29 Aug 2026 22:44:54 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org TPL max size for Rockchip PX30 SoC is very low, but 10240 bytes are enough to store in two DDR configuration parameters sets if option CONFIG_RAM_ROCKCHIP_DEBUG is deselected. The approach is trivial: apply supported DDR config sets in a predefined order (DDR4, LPDDR2, LPDDR3, DDR3) stopping at the first one that makes SDRAM initialization function to complete with success. If a smarter cleverer or more reliable approach exists, suggestions are welcome. The patches have been tested on two boards, one equipped with DDR3 and the other with DDR4. All possible sets selections have been tested, even with orders different from predefined one (e.g. DDR3, LPDDR2, LPDDR3, DDR4). It would be useful if further tests will be run on other PX30 based boards. The patches does not affect binary code of TPL for any of the existing U-Boot configurations. The first patch improves clarity of DDR type support selection for Rockchip SoCs at Kconfig level. Not all the DDR type config options named in the Kconfig are supported by each one of the Rockchip SoCs. Moreover, the LPDDR4 option has a different meaning in the context of the RK3399 SoC than in the RV1126 one. Thus, split options with ad-hoc specific help sections and use depends on conditionals. The second patch splits RV1126 options (at most one should be selected) from PX30 options (more options can be selected), and adds DDR3 option for PX30. The PX30 sdram driver includes all of the selected DDR type sets or just the DDR3 one if none is selected: not like it too much but I preferred to preserve default fallback behavior (include DDR3 support if no option is selected) to avoid modifing boards configs relying on it. The parameters sets are applied as already described. Signed-off-by: Massimo Pegorer --- Massimo Pegorer (2): ram: rockchip: improve ddr type configs selection ram: rockchip: px30: allow multiple DDR types selection drivers/ram/rockchip/Kconfig | 78 ++++++++++++++++++++++++++++++++++++--- drivers/ram/rockchip/sdram_px30.c | 35 +++++++++++------- 2 files changed, 93 insertions(+), 20 deletions(-) --- base-commit: 964ad5b5c91b7be56e443e899d7f873e6aa8c9fc change-id: 20260828-ddr-multi-2c4fd64344c8 Best regards, -- Massimo Pegorer