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Sat, 29 Aug 2026 10:03:31 -0700 (PDT) Received: from [127.0.1.1] ([151.51.168.243]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482fbb32ce2sm12163133f8f.33.2026.08.29.10.03.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Aug 2026 10:03:30 -0700 (PDT) Sender: Massimo Pegorer From: Massimo Pegorer Date: Sat, 29 Aug 2026 19:03:12 +0200 Subject: [PATCH 2/2] ram: rockchip: px30: allow multiple DDR types selection MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260829-ddr-multi-v1-2-c0c7837aed20@gmail.com> References: <20260829-ddr-multi-v1-0-c0c7837aed20@gmail.com> In-Reply-To: <20260829-ddr-multi-v1-0-c0c7837aed20@gmail.com> To: Simon Glass , u-boot@lists.u-boot-project.org Cc: Quentin Schulz , Kever Yang , Tom Rini , Massimo Pegorer X-Mailer: b4 0.15.2 X-Mailman-Approved-At: Sat, 29 Aug 2026 22:44:54 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Allow the inclusion of more than one DDR parameters set in the PX30 SDRAM driver. The driver applies included sets in a predefined order (DDR4, LPDDR2, LPDDR3, DDR3), stopping at the first one that makes SDRAM initialization function to complete with success. The default fallback behaviour is preserved: if no DDR configuration option is selected, DDR3 parameters set is included. Due to limited PX30 TPL maximum size, including support for more than one DDR type requires disabling some configuration options such as CONFIG_RAM_ROCKCHIP_DEBUG. Signed-off-by: Massimo Pegorer --- drivers/ram/rockchip/Kconfig | 67 +++++++++++++++++++++++++++++++-------- drivers/ram/rockchip/sdram_px30.c | 35 ++++++++++++-------- 2 files changed, 74 insertions(+), 28 deletions(-) diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig index 61a3193b3f5..d74980402ad 100644 --- a/drivers/ram/rockchip/Kconfig +++ b/drivers/ram/rockchip/Kconfig @@ -24,38 +24,77 @@ config RAM_ROCKCHIP_DEBUG This is an option for developers to understand the ram drivers initialization, configurations and etc. +config RAM_ROCKCHIP_DDR3 + bool "DDR3 support for Rockchip SoCs" + depends on ROCKCHIP_PX30 + help + Enable DDR3 sdram support on Rockchip SoCs. + + Note that enabling support for multiple DDR/LPDDR types may cause TPL + to exceed its maximum size constraint (TPL_MAX_SIZE), depending on + other configuration options selection (such as RAM_ROCKCHIP_DEBUG). + + The driver applies selected sdram parameters sets in the following + order - DDR4 LPDDR2 LPDDR3 DDR3 - stopping at first set that makes + sdram_init_detect() to complete successfully. + + If no DDR/LPDDR option is selected, DDR3 sdram support is enabled by + default for backward compatibility with existing board configurations. + Therefore this option is only useful for multiple DDR/LPDDR types + selection. + config RAM_ROCKCHIP_DDR4 bool "DDR4 support for Rockchip SoCs" - depends on ROCKCHIP_PX30 || ROCKCHIP_RV1126 + depends on ROCKCHIP_PX30 help - This enables DDR4 sdram support instead of the default DDR3 support - on Rockchip SoCs. + Enable DDR4 sdram support on Rockchip SoCs. - Note that even if multiple DDR/LPDDR types are selected, support is - enabled only for the selected one that comes first in the following - list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3. + Note that enabling support for multiple DDR/LPDDR types may cause TPL + to exceed its maximum size constraint (TPL_MAX_SIZE), depending on + other configuration options selection (such as RAM_ROCKCHIP_DEBUG). + + The driver applies selected sdram parameters sets in the following + order - DDR4 LPDDR2 LPDDR3 DDR3 - stopping at first set that makes + sdram_init_detect() to complete successfully. config RAM_ROCKCHIP_LPDDR2 bool "LPDDR2 support for Rockchip SoCs" depends on ROCKCHIP_PX30 help - This enables LPDDR2 sdram support instead of the default DDR3 support - on Rockchip SoCs. + Enable LPDDR2 sdram support on Rockchip SoCs. - Note that even if multiple DDR/LPDDR types are selected, support is - enabled only for the selected one that comes first in the following - list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3. + Note that enabling support for multiple DDR/LPDDR types may cause TPL + to exceed its maximum size constraint (TPL_MAX_SIZE), depending on + other configuration options selection (such as RAM_ROCKCHIP_DEBUG). + + The driver applies selected sdram parameters sets in the following + order - DDR4 LPDDR2 LPDDR3 DDR3 - stopping at first set that makes + sdram_init_detect() to complete successfully. config RAM_ROCKCHIP_LPDDR3 bool "LPDDR3 support for Rockchip SoCs" depends on ROCKCHIP_PX30 help - This enables LPDDR3 sdram support instead of the default DDR3 support + Enable LPDDR3 sdram support on Rockchip SoCs. + + Note that enabling support for multiple DDR/LPDDR types may cause TPL + to exceed its maximum size constraint (TPL_MAX_SIZE), depending on + other configuration options selection (such as RAM_ROCKCHIP_DEBUG). + + The driver applies selected sdram parameters sets in the following + order - DDR4 LPDDR2 LPDDR3 DDR3 - stopping at first set that makes + sdram_init_detect() to complete successfully. + +config RAM_ROCKCHIP_DDR4 + bool "DDR4 support for Rockchip SoCs" + depends on ROCKCHIP_RV1126 + help + This enables DDR4 sdram support instead of the default DDR3 support on Rockchip SoCs. Note that even if multiple DDR/LPDDR types are selected, support is enabled only for the selected one that comes first in the following - list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3. + list: LPDDR4, DDR4, DDR3. config RAM_ROCKCHIP_LPDDR4 depends on ROCKCHIP_RV1126 @@ -66,7 +105,7 @@ config RAM_ROCKCHIP_LPDDR4 Note that even if multiple DDR/LPDDR types are selected, support is enabled only for the selected one that comes first in the following - list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3. + list: LPDDR4, DDR4, DDR3. config RAM_ROCKCHIP_LPDDR4 bool "LPDDR4 support for Rockchip SoCs" diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index 37e62120504..ac9f5827d1d 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -126,11 +126,17 @@ struct dram_info dram_info; struct px30_sdram_params sdram_configs[] = { #if defined(CONFIG_RAM_ROCKCHIP_DDR4) #include "sdram-px30-ddr4-detect-333.inc" -#elif defined(CONFIG_RAM_ROCKCHIP_LPDDR2) +#endif +#if defined(CONFIG_RAM_ROCKCHIP_LPDDR2) #include "sdram-px30-lpddr2-detect-333.inc" -#elif defined(CONFIG_RAM_ROCKCHIP_LPDDR3) +#endif +#if defined(CONFIG_RAM_ROCKCHIP_LPDDR3) #include "sdram-px30-lpddr3-detect-333.inc" -#else +#endif +#if defined(CONFIG_RAM_ROCKCHIP_DDR3) || \ + (!defined(CONFIG_RAM_ROCKCHIP_DDR4) && \ + !defined(CONFIG_RAM_ROCKCHIP_LPDDR2) && \ + !defined(CONFIG_RAM_ROCKCHIP_LPDDR3)) #include "sdram-px30-ddr3-detect-333.inc" #endif }; @@ -682,19 +688,11 @@ out: return ret; } -struct px30_sdram_params - *get_default_sdram_config(void) -{ - sdram_configs[0].skew = &skew; - - return &sdram_configs[0]; -} - /* return: 0 = success, other = fail */ int sdram_init(void) { struct px30_sdram_params *sdram_params; - int ret = 0; + int ret, i = 0; dram_info.phy = (void *)DDR_PHY_BASE_ADDR; dram_info.pctl = (void *)DDRC_BASE_ADDR; @@ -704,12 +702,21 @@ int sdram_init(void) dram_info.ddr_grf = (void *)DDR_GRF_BASE_ADDR; dram_info.pmugrf = (void *)PMUGRF_BASE_ADDR; - sdram_params = get_default_sdram_config(); - ret = sdram_init_detect(&dram_info, sdram_params); + do { + sdram_configs[i].skew = &skew; + sdram_params = &sdram_configs[i]; + ret = sdram_init_detect(&dram_info, sdram_params); + } while (ret && ++i < ARRAY_SIZE(sdram_configs)); if (ret) goto error; + if (ARRAY_SIZE(sdram_configs) > 1) { + printascii("Applied sdram config: "); + printdec(i); + printascii("\n"); + } + sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base, 0); printascii("out\n"); -- 2.34.1