From: JunWei Li <vae1207@gmail.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, chenhuacai@canaan-creative.com,
JunWei Li <vae1207@gmail.com>
Subject: [PATCH 3/3] tests/qtest: add k230-pmu-test
Date: Sat, 29 Aug 2026 10:02:29 +0800 [thread overview]
Message-ID: <20260829020229.389742-4-vae1207@gmail.com> (raw)
In-Reply-To: <20260829020229.389742-1-vae1207@gmail.com>
Add qtest coverage for the K230 PMU: register reset values, write masks, interrupt triggering and W1C clearing through the input pads, and PAD70/PAD71 output behaviour.
Signed-off-by: JunWei Li <vae1207@gmail.com>
---
tests/qtest/k230-pmu-test.c | 136 ++++++++++++++++++++++++++++++++++++
tests/qtest/meson.build | 3 +-
2 files changed, 138 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/k230-pmu-test.c
diff --git a/tests/qtest/k230-pmu-test.c b/tests/qtest/k230-pmu-test.c
new file mode 100644
index 0000000000..9f24b18f19
--- /dev/null
+++ b/tests/qtest/k230-pmu-test.c
@@ -0,0 +1,136 @@
+/*
+ * QTest for the K230 PMU Unit.
+ *
+ * Copyright (c) 2026 LiJunWei <vae1207@gmail.com>
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * K230 Technical Reference Manual V0.3.1 (2024-11-18):
+ * https://github.com/revyos/external-docs/blob/master/K230/en-us/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+#include "hw/misc/k230_pmu.h"
+
+#define PMU_BASE 0x91000000
+
+static void test_reset_values(void)
+{
+ QTestState *qts = qtest_init("-machine k230");
+
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT0_TO_CTL * 4), ==,
+ 0xfff);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT1_TO_CTL * 4), ==,
+ 0xfff);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT0_TO_CPU * 4), ==, 0);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_DETECT_EN * 4), ==,
+ 0x810);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_DETECT_TYP * 4), ==, 0);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_DETECT_CLR * 4), ==, 0);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_LONG_PRESS_TRIGGER * 4),
+ ==, 0x17700);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_LONG_PRESS_SHUTDOWN * 4),
+ ==, 0x4e200);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_SHORT_PRESS_TRIGGER * 4),
+ ==, 0x3e800);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_LEVEL_DEBOUNCE * 4), ==,
+ 0x100);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_EDGE_NUMBER * 4), ==, 0x1);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_SYSCTRL * 4), ==, 0x1);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_OUT_DELAY_SET * 4), ==,
+ 0x1100640);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_IO_CFG0 * 4), ==, 0x1124);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_IO_CFG6 * 4), ==, 0x10a4);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_IO_CFG7 * 4), ==, 0x1084);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_NORMAL_TIMER_VAL * 4), ==,
+ 0x780);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_OUT_EVENT_CTRL * 4), ==,
+ 0x5c);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_OUT_LOGIC_CTRL * 4), ==,
+ 0x2);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_STATE * 4), ==, 0);
+
+ qtest_quit(qts);
+}
+
+static void test_write_masks(void)
+{
+ QTestState *qts = qtest_init("-machine k230");
+
+ /* Reserved bits are write-ignored and read as zero. */
+ qtest_writel(qts, PMU_BASE + R_INT_DETECT_EN * 4, 0xffffffff);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_DETECT_EN * 4), ==,
+ 0x1fff);
+ qtest_writel(qts, PMU_BASE + R_INT_DETECT_TYP * 4, 0xffffffff);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_DETECT_TYP * 4), ==,
+ 0x1fffff);
+ qtest_writel(qts, PMU_BASE + R_IO_CFG0 * 4, 0xffffffff);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_IO_CFG0 * 4), ==, 0x3def);
+ qtest_writel(qts, PMU_BASE + R_SYSCTRL * 4, 0xffffffff);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_SYSCTRL * 4), ==, 0x3);
+
+ /* PMU_INT_STATE_REG is read-only. */
+ qtest_writel(qts, PMU_BASE + R_INT_STATE * 4, 0xffffffff);
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_STATE * 4), ==, 0);
+
+ qtest_quit(qts);
+}
+
+static void test_interrupt_clear(void)
+{
+ QTestState *qts = qtest_init("-machine k230");
+
+ qtest_irq_intercept_out_named(qts, "/machine/soc/k230-pmu",
+ "sysbus-irq");
+
+ /*
+ * PAD68 (input 4) edge/level detection is enabled by default
+ * (PMU_INT_DETECT_EN bit 4). Raise the input and gate the
+ * corresponding interrupt through PMU_INT0_TO_CPU.
+ */
+ qtest_writel(qts, PMU_BASE + R_INT0_TO_CPU * 4, BIT(4));
+ qtest_set_irq_in(qts, "/machine/soc/k230-pmu", NULL, 4, 1);
+
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_STATE * 4) & BIT(4),
+ ==, BIT(4));
+ g_assert_cmpuint(qtest_get_irq(qts, 0), ==, 1);
+
+ /* CLR bit 1 clears the int4 edge/level state (W1C). */
+ qtest_writel(qts, PMU_BASE + R_INT_DETECT_CLR * 4, BIT(1));
+ g_assert_cmphex(qtest_readl(qts, PMU_BASE + R_INT_STATE * 4) & BIT(4),
+ ==, 0);
+ g_assert_cmpuint(qtest_get_irq(qts, 0), ==, 0);
+
+ qtest_quit(qts);
+}
+
+static void test_pad_outputs(void)
+{
+ QTestState *qts = qtest_init("-machine k230");
+
+ qtest_irq_intercept_out_named(qts, "/machine/soc/k230-pmu",
+ "sysbus-irq");
+
+ /* PAD70/PAD71 follow the PMU_SYSCTRL_REG to_ctrl bits. */
+ qtest_writel(qts, PMU_BASE + R_SYSCTRL * 4, 0x0);
+ g_assert_cmpuint(qtest_get_irq(qts, 1), ==, 0);
+ g_assert_cmpuint(qtest_get_irq(qts, 2), ==, 0);
+
+ qtest_writel(qts, PMU_BASE + R_SYSCTRL * 4, 0x3);
+ g_assert_cmpuint(qtest_get_irq(qts, 1), ==, 1);
+ g_assert_cmpuint(qtest_get_irq(qts, 2), ==, 1);
+
+ qtest_quit(qts);
+}
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+
+ qtest_add_func("/k230/pmu/reset-values", test_reset_values);
+ qtest_add_func("/k230/pmu/write-masks", test_write_masks);
+ qtest_add_func("/k230/pmu/interrupt-clear", test_interrupt_clear);
+ qtest_add_func("/k230/pmu/pad-outputs", test_pad_outputs);
+
+ return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 56ff860e21..daa5b6a284 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -297,7 +297,8 @@ qtests_riscv64 = ['riscv-csr-test'] + \
(config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and
config_all_devices.has_key('CONFIG_RISCV_IOMMU') ?
['iommu-riscv-test'] : []) + \
- (config_all_devices.has_key('CONFIG_K230') ? ['k230-wdt-test'] : [])
+ (config_all_devices.has_key('CONFIG_K230') ?
+ ['k230-wdt-test', 'k230-pmu-test'] : [])
qtests_hexagon = ['boot-serial-test']
--
2.20.1
prev parent reply other threads:[~2026-08-29 4:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-29 2:02 [PATCH 0/3] hw/misc: add K230 PMU device model JunWei Li
2026-08-29 2:02 ` [PATCH 1/3] hw/misc: add K230 PMU device JunWei Li
2026-08-29 2:02 ` [PATCH 2/3] hw/riscv: wire up K230 PMU in the SoC JunWei Li
2026-08-29 2:02 ` JunWei Li [this message]
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