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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8569ff701d5sm2455900b3a.25.2026.08.30.09.03.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Aug 2026 09:03:42 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza , Max Chou , Weiwei Li , Liu Zhiwei , Chao Liu Subject: [PATCH v3 0/6] target/riscv: Add SiFive Xsfvqmaccdod/Xsfvqmaccqoq int8 matmul extensions Date: Mon, 31 Aug 2026 00:03:29 +0800 Message-ID: <20260830160335.3441069-1-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org This patchset adds SiFive's custom int8 matrix-multiply vector extensions Xsfvqmaccdod and Xsfvqmaccqoq. Each extension provides 4 signedness variants (unsigned/unsigned, signed/signed, unsigned/signed, signed/unsigned) for a total of 8 instructions: sf.vqmacc{u,,us,su}.{4x8x4,2x8x2}. The toolchains support Xsfvqmaccdod/Xsfvqmaccqoq extensions: - LLVM 18.1.0 - llvm/llvm-project#68295, commit d1985e3d1fed, merged 2023-10-20. https://github.com/llvm/llvm-project/pull/68295 - GCC 15 - commit 139bd3198a73 ("RISC-V: Add the mini support for SiFive extensions"), 2024-11-17. References: - SiFive Int8 Matrix Multiplication Extensions Specification https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification Changes since v2:<20260812174417.2468981-1-max.chou@sifive.com> - Rebase to riscv-to-apply.next branch (commit aee18ec) - Modified patch 5 to align the new disas flow Changes since v1:<20260721122034.1567146-1-max.chou@sifive.com> - Rebase to master branch (commit 84f0721) - Reformat riscv_multi_ext_implied_rules to list one rule per line before adding XSFVQMACCDOD_IMPLIED/XSFVQMACCQOQ_IMPLIED, so future additions to the array are a pure append instead of reflowing whatever line they land on. Split out into its own patch. (Thanks for Daniel Henrique Barboza's suggestion) - Move the SiFive int8 matmul helper out of the shared vector_helper.c and into a new target/riscv/tcg/xsf_helper.c, so vendor-specific code no longer lives in common vector-helper code. (Thanks for Daniel Henrique Barboza's suggestion) rnax Frank Chang (2): target/riscv/cpu: Add SiFive custom int8 matmul extension implied rules target/riscv: rvv: Add SiFive custom int8 matmul instructions Jason Chien (1): disas/riscv: Add disassembler support for Xsfvqmaccdod/Xsfvqmaccqoq Max Chou (3): target/riscv: Add cfg property for SiFive int8 matmul extensions target/riscv/cpu: List one implied-ext rule per line tests/tcg/riscv64: Add tests for SiFive int8 matmul extensions MAINTAINERS | 10 + disas/meson.build | 3 +- disas/riscv-xsf-op.c.inc | 11 + disas/riscv-xsf.c | 49 ++++ disas/riscv-xsf.h | 16 ++ disas/riscv.c | 2 + disas/riscv.h | 1 + target/riscv/cpu.c | 80 ++++-- target/riscv/cpu_cfg.h | 5 + target/riscv/cpu_cfg_fields.h.inc | 2 + target/riscv/helper.h | 10 + target/riscv/meson.build | 1 + target/riscv/tcg/insn_trans/trans_xsf.c.inc | 98 ++++++++ target/riscv/tcg/meson.build | 1 + target/riscv/tcg/tcg-cpu.c | 16 ++ target/riscv/tcg/translate.c | 3 + target/riscv/tcg/xsf_helper.c | 87 +++++++ target/riscv/xsf.decode | 30 +++ tests/tcg/riscv64/Makefile.softmmu-target | 7 + tests/tcg/riscv64/test-xsfvqmacc.S | 260 ++++++++++++++++++++ 20 files changed, 677 insertions(+), 15 deletions(-) create mode 100644 disas/riscv-xsf-op.c.inc create mode 100644 disas/riscv-xsf.c create mode 100644 disas/riscv-xsf.h create mode 100644 target/riscv/tcg/insn_trans/trans_xsf.c.inc create mode 100644 target/riscv/tcg/xsf_helper.c create mode 100644 target/riscv/xsf.decode create mode 100644 tests/tcg/riscv64/test-xsfvqmacc.S -- 2.43.0