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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8569ff701d5sm2455900b3a.25.2026.08.30.09.03.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Aug 2026 09:03:45 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza , Max Chou , Weiwei Li , Liu Zhiwei , Chao Liu , Alistair Francis Subject: [PATCH v3 1/6] target/riscv: Add cfg property for SiFive int8 matmul extensions Date: Mon, 31 Aug 2026 00:03:30 +0800 Message-ID: <20260830160335.3441069-2-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260830160335.3441069-1-max.chou@sifive.com> References: <20260830160335.3441069-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Add the CPU config properties for SiFive's custom int8 matrix multiply vector extensions: - Xsfvqmaccdod: 2x8x2 int8 matrix-multiply-accumulate operations - Xsfvqmaccqoq: 4x8x4 int8 matrix-multiply-accumulate operations All instructions of these extensions require the Zve32x extension to be present whenever either extension is enabled. Validate this in riscv_cpu_validate_vendor_ext() alongside the existing vector extension validation in riscv_cpu_validate_set_extensions(). Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Max Chou --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg_fields.h.inc | 2 ++ target/riscv/tcg/tcg-cpu.c | 16 ++++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 61109672d60..b4e34daf8ec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -299,6 +299,8 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop), ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov), ISA_EXT_DATA_ENTRY(xmipslsp, PRIV_VERSION_1_12_0, ext_xmipslsp), + ISA_EXT_DATA_ENTRY(xsfvqmaccdod, PRIV_VERSION_1_13_0, ext_xsfvqmaccdod), + ISA_EXT_DATA_ENTRY(xsfvqmaccqoq, PRIV_VERSION_1_13_0, ext_xsfvqmaccqoq), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc index f91c780299c..0f3bda1331c 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -159,6 +159,8 @@ BOOL_FIELD(ext_xmipscbop) BOOL_FIELD(ext_xmipscmov) BOOL_FIELD(ext_xmipslsp) BOOL_FIELD(ext_xlrbr) +BOOL_FIELD(ext_xsfvqmaccdod) +BOOL_FIELD(ext_xsfvqmaccqoq) BOOL_FIELD(big_endian) BOOL_FIELD(mmu) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 54f1b66216c..bdb6dc6ab3f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -418,6 +418,16 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, } } +static void riscv_cpu_validate_vendor_ext(RISCVCPU *cpu, Error **errp) +{ + if ((cpu->cfg.ext_xsfvqmaccdod || cpu->cfg.ext_xsfvqmaccqoq) && + !cpu->cfg.ext_zve32x) { + error_setg(errp, "Xsfvqmaccdod/Xsfvqmaccqoq extensions require " + "Zve32x extension"); + return; + } +} + static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env = &cpu->env; @@ -795,6 +805,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + riscv_cpu_validate_vendor_ext(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + if (mcc->def->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { error_setg(errp, "svukte is not supported for RV32"); return; -- 2.43.0