From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
Max Chou <max.chou@sifive.com>, Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Chao Liu <chao.liu@processmission.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v3 2/6] target/riscv/cpu: List one implied-ext rule per line
Date: Mon, 31 Aug 2026 00:03:31 +0800 [thread overview]
Message-ID: <20260830160335.3441069-3-max.chou@sifive.com> (raw)
In-Reply-To: <20260830160335.3441069-1-max.chou@sifive.com>
Every entry added to riscv_multi_ext_implied_rules[] currently has to
reflow whatever line it lands on, since entries are packed several
per line. List one rule per line instead so future additions are a
pure append.
Suggested-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 58 +++++++++++++++++++++++++++++++++++-----------
1 file changed, 44 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b4e34daf8ec..af61a1ab48d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2909,20 +2909,50 @@ RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
};
RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
- &ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED,
- &ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED,
- &ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED,
- &ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED,
- &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED,
- &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED,
- &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED,
- &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, &ZVE64X_IMPLIED,
- &ZVFBFA_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
- &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
- &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
- &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SHA_IMPLIED,
- &SSCFG_IMPLIED, &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED,
- &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED,
+ &ZCB_IMPLIED,
+ &ZCD_IMPLIED,
+ &ZCE_IMPLIED,
+ &ZCF_IMPLIED,
+ &ZCMP_IMPLIED,
+ &ZCMT_IMPLIED,
+ &ZDINX_IMPLIED,
+ &ZFA_IMPLIED,
+ &ZFBFMIN_IMPLIED,
+ &ZFH_IMPLIED,
+ &ZFHMIN_IMPLIED,
+ &ZFINX_IMPLIED,
+ &ZHINX_IMPLIED,
+ &ZHINXMIN_IMPLIED,
+ &ZICNTR_IMPLIED,
+ &ZIHPM_IMPLIED,
+ &ZK_IMPLIED,
+ &ZKN_IMPLIED,
+ &ZKS_IMPLIED,
+ &ZVBB_IMPLIED,
+ &ZVE32F_IMPLIED,
+ &ZVE32X_IMPLIED,
+ &ZVE64D_IMPLIED,
+ &ZVE64F_IMPLIED,
+ &ZVE64X_IMPLIED,
+ &ZVFBFA_IMPLIED,
+ &ZVFBFMIN_IMPLIED,
+ &ZVFBFWMA_IMPLIED,
+ &ZVFH_IMPLIED,
+ &ZVFHMIN_IMPLIED,
+ &ZVKN_IMPLIED,
+ &ZVKNC_IMPLIED,
+ &ZVKNG_IMPLIED,
+ &ZVKNHB_IMPLIED,
+ &ZVKS_IMPLIED,
+ &ZVKSC_IMPLIED,
+ &ZVKSG_IMPLIED,
+ &SHA_IMPLIED,
+ &SSCFG_IMPLIED,
+ &SUPM_IMPLIED,
+ &SSPM_IMPLIED,
+ &SMCTR_IMPLIED,
+ &SSCTR_IMPLIED,
+ &SSSTATEEN_IMPLIED,
NULL
};
--
2.43.0
next prev parent reply other threads:[~2026-08-30 16:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-30 16:03 [PATCH v3 0/6] target/riscv: Add SiFive Xsfvqmaccdod/Xsfvqmaccqoq int8 matmul extensions Max Chou
2026-08-30 16:03 ` [PATCH v3 1/6] target/riscv: Add cfg property for SiFive " Max Chou
2026-08-30 16:03 ` Max Chou [this message]
2026-08-30 16:03 ` [PATCH v3 3/6] target/riscv/cpu: Add SiFive custom int8 matmul extension implied rules Max Chou
2026-08-30 16:03 ` [PATCH v3 4/6] target/riscv: rvv: Add SiFive custom int8 matmul instructions Max Chou
2026-08-30 16:03 ` [PATCH v3 5/6] disas/riscv: Add disassembler support for Xsfvqmaccdod/Xsfvqmaccqoq Max Chou
2026-09-07 4:12 ` Alistair Francis
2026-08-30 16:03 ` [PATCH v3 6/6] tests/tcg/riscv64: Add tests for SiFive int8 matmul extensions Max Chou
2026-09-07 4:22 ` Alistair Francis
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