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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8569ff701d5sm2455900b3a.25.2026.08.30.09.03.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Aug 2026 09:03:51 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza , Max Chou , Weiwei Li , Liu Zhiwei , Chao Liu , Frank Chang , Alistair Francis Subject: [PATCH v3 3/6] target/riscv/cpu: Add SiFive custom int8 matmul extension implied rules Date: Mon, 31 Aug 2026 00:03:32 +0800 Message-ID: <20260830160335.3441069-4-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260830160335.3441069-1-max.chou@sifive.com> References: <20260830160335.3441069-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=max.chou@sifive.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Frank Chang Add SiFive custom int8 matmul extension implied rules to enable the implied extensions of SiFive custom int8 matmul extension recursively. Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Max Chou --- target/riscv/cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index af61a1ab48d..4263b7de241 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2902,6 +2902,24 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = { }, }; +static RISCVCPUImpliedExtsRule XSFVQMACCDOD_IMPLIED = { + .ext = CPU_CFG_OFFSET(ext_xsfvqmaccdod), + .implied_multi_exts = { + CPU_CFG_OFFSET(ext_zve32x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule XSFVQMACCQOQ_IMPLIED = { + .ext = CPU_CFG_OFFSET(ext_xsfvqmaccqoq), + .implied_multi_exts = { + CPU_CFG_OFFSET(ext_zve32x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = { &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, @@ -2953,6 +2971,8 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { &SMCTR_IMPLIED, &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED, + &XSFVQMACCDOD_IMPLIED, + &XSFVQMACCQOQ_IMPLIED, NULL }; -- 2.43.0