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Mon, 31 Aug 2026 05:36:59 +0000 From: Kane Chen To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Troy Lee , Kane Chen Subject: [PATCH v1 0/2] hw/misc/aspeed_sbc: Fix ABR and secure boot state reporting Thread-Topic: [PATCH v1 0/2] hw/misc/aspeed_sbc: Fix ABR and secure boot state reporting Thread-Index: AQHdOQq9/R0jZV18Akai2f8RyjRuSA== Date: Mon, 31 Aug 2026 05:36:59 +0000 Message-ID: <20260831053658.462203-1-kane_chen@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SI6PR06MB7631:EE_|KUXPR06MB8654:EE_ x-ms-office365-filtering-correlation-id: ad425e36-b836-4332-4024-08df0721e080 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=kane_chen@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The ASPEED Secure Boot Controller (SBC) model currently derives its=0A= eMMC ABR (Alternate Boot Recovery) and secure boot enable bits from=0A= fixed "emmc-abr"/"signing-settings" machine properties. The logic=0A= that reflects these properties into R_STATUS is broken, so neither=0A= bit can ever actually be reported as enabled, and for secure boot=0A= this also leaves R_STATUS and R_QSR inconsistent with each other.=0A= =0A= This series replaces both properties with logic that derives the ABR=0A= and secure boot state directly from the relevant OTP configuration=0A= straps, matching how the real hardware determines these settings.=0A= =0A= Any feedback or suggestions are appreciated!=0A= =0A= Kane-Chen-AS (2):=0A= hw/misc/aspeed_sbc: Derive ABR state from OTP config straps=0A= hw/misc/aspeed_sbc: Derive secure boot state from OTP config straps=0A= =0A= include/hw/misc/aspeed_sbc.h | 3 --=0A= hw/misc/aspeed_sbc.c | 69 +++++++++++++++++++++++++++++-------=0A= 2 files changed, 56 insertions(+), 16 deletions(-)=0A= =0A= -- =0A= 2.43.0=0A=