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envelope-from=saif.abrar@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Saif Abrar Get the current link-status from PCIE macro. Extract link-speed and link-width from the link-status and set in the DLP training control (PCIE_DLP_TCR) register. Signed-off-by: Saif Abrar Reviewed-by: Cédric Le Goater Reviewed-by: Michael S. Tsirkin Reviewed-by: Caleb Schlossin Reviewed-by: Aditya Gupta --- hw/pci-host/pnv_phb4.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 87446aedc8..56952a6200 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -518,7 +518,7 @@ static uint32_t is_link_active(PnvPHB4 *phb) PCIDevice *pdev = pci_find_device(pci->bus, 0, 0); uint32_t exp_offset = get_exp_offset(pdev); - return (be16_to_cpu(pnv_phb4_rc_config_read(phb, + return (be32_to_cpu(pnv_phb4_rc_config_read(phb, exp_offset + PCI_EXP_LNKSTA, 4)) & PCI_EXP_LNKSTA_DLLLA); } @@ -865,6 +865,7 @@ uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) PCIDevice *pdev = pci_find_device(pci->bus, 0, 0); uint32_t exp_base = get_exp_offset(pdev); uint64_t val; + uint32_t v, lnkstatus; if ((off & 0xfffc) == PHB_CONFIG_DATA) { return pnv_phb4_config_read(phb, off & 0x3, size); @@ -926,10 +927,27 @@ uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) val |= PHB_PCIE_SCR_PLW_X16; /* RO bit */ break; - /* Link training always appears trained */ case PHB_PCIE_DLP_TRAIN_CTL: - /* TODO: Do something sensible with speed ? */ + /* Get the current link-status from PCIE */ + lnkstatus = be32_to_cpu(pnv_phb4_rc_config_read(phb, + exp_base + PCI_EXP_LNKSTA, 4)); + + /* Extract link-speed from the link-status */ + v = lnkstatus & PCI_EXP_LNKSTA_CLS; + + /* Link training always appears trained */ val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; + + /* Set the current link-speed at the LINK_SPEED position */ + val = SETFIELD(PHB_PCIE_DLP_LINK_SPEED, val, v); + + /* + * Extract link-width from the link-status, + * after shifting the required bitfields. + */ + v = (lnkstatus & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; + /* Set the current link-width at the LINK_WIDTH position */ + val = SETFIELD(PHB_PCIE_DLP_LINK_WIDTH, val, v); return val; /* @@ -952,7 +970,7 @@ uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) * convert the value back to host format. * Clear the Presence-status active low bit. */ - if (be16_to_cpu(pnv_phb4_rc_config_read(phb, exp_base + PCI_EXP_SLTSTA, + if (be32_to_cpu(pnv_phb4_rc_config_read(phb, exp_base + PCI_EXP_SLTSTA, 4)) & PCI_EXP_SLTSTA_PDS) { val &= ~PHB_PCIE_HPSTAT_PRESENCE; -- 2.52.0