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Tue, 1 Sep 2026 08:15:32 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v4 0/4] Add ASPEED ACRY RSA model for the AST2600 Thread-Topic: [PATCH v4 0/4] Add ASPEED ACRY RSA model for the AST2600 Thread-Index: AQHdOeoOg+VpFs4KlU2yRpYhi5f9sQ== Date: Tue, 1 Sep 2026 08:15:32 +0000 Message-ID: <20260901081531.898176-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR06MB4980:EE_|TYUPR06MB6151:EE_ x-ms-office365-filtering-correlation-id: 869f83ee-00ec-466f-75d1-08df08013164 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series adds a model of the ASPEED ACRY engine found on the AST2600=0A= SoC, wires it into the SoC, and adds a qtest.=0A= =0A= The ACRY engine performs RSA modular exponentiation (c =3D m^e mod n). It= =0A= DMAs the operands (data, exponent, and modulus) from guest DRAM and writes= =0A= the result to a dedicated 64 KiB SRAM region.=0A= =0A= Guest firmware uses the engine for RSA signature verification during boot.= =0A= Without a model, the guest starts the engine and waits indefinitely for a= =0A= completion interrupt, causing the boot to hang.=0A= =0A= The model uses QEMU's generic akcipher API to perform raw (unpadded) RSA.= =0A= Raw RSA is currently supported only by the libgcrypt backend, which can be= =0A= enabled alongside gnutls with -Dgcrypt=3Denabled, so a build does not have = to=0A= choose between the two. When raw RSA is unavailable, the engine still=0A= completes and raises its interrupt, but returns an all-zero result. This=0A= allows the guest's signature verification to fail cleanly instead of=0A= hanging. The qtest is skipped when the selected crypto backend does not=0A= support raw RSA.=0A= =0A= Although the hardware documentation describes both RSA and ECDSA support,= =0A= ECDSA is known to be broken on this hardware and is therefore not modeled.= =0A= =0A= v1:=0A= 1. Add ASPEED ACRY RSA model for the AST2600=0A= 2. Add qtest for AST2600 ASPEED ACRY RSA model=0A= =0A= v2:=0A= 1. squash "Add the ACRY model to AspeedSoCState" into "Wire up the ACRY=0A= model"=0A= 2. wrap the ACRY SRAM in a container mapped at offset 0 so the device=0A= addresses it by relative offset (drop the "sram-base" property)=0A= 3. build the scattered SRAM byte offsets on the fly instead of caching=0A= them in per-instance lookup tables=0A= 4. write the result with address_space_stl_le() and check the MemTxResult= =0A= =0A= v3:=0A= 1. Return early when the DMA read of the operand buffer fails =0A= 2. Replace g_printerr with g_test_skip=0A= =0A= v4:=0A= 1. Remove unused macros.=0A= 2. Dynamically allocate data and src_buf to reduce stack usage in aspeed_= acry_do_rsa().=0A= 3. Add a helper function to clear the result when aspeed_acry_do_rsa() fa= ils.=0A= 4. Add bounds checking to aspeed_acry_operand_offset() and replace magic = numbers with=0A= compile-time constants.=0A= =0A= Jamin Lin (4):=0A= hw/misc/aspeed_acry: Add ASPEED ACRY model=0A= hw/arm/aspeed_ast2600: Introduce the ACRY SRAM=0A= hw/arm/aspeed_ast2600: Wire up the ACRY model=0A= tests/qtest/aspeed-acry-test: Add RSA ModExp tests=0A= =0A= include/hw/arm/aspeed_soc.h | 4 +=0A= include/hw/misc/aspeed_acry.h | 39 +++=0A= hw/arm/aspeed_ast2600.c | 34 +++=0A= hw/misc/aspeed_acry.c | 481 +++++++++++++++++++++++++++++++++=0A= tests/qtest/aspeed-acry-test.c | 406 ++++++++++++++++++++++++++++=0A= hw/misc/meson.build | 1 +=0A= hw/misc/trace-events | 6 +=0A= tests/qtest/meson.build | 5 +-=0A= 8 files changed, 975 insertions(+), 1 deletion(-)=0A= create mode 100644 include/hw/misc/aspeed_acry.h=0A= create mode 100644 hw/misc/aspeed_acry.c=0A= create mode 100644 tests/qtest/aspeed-acry-test.c=0A= =0A= -- =0A= 2.53.0=0A=